Colin Schmidt
ad81d95751
add run-asm-{p,pt,v}-tests targets for convenience
2016-02-24 19:49:35 -08:00
John Wright
b04cd545b6
pass base SCR address to SCRFile for address calculation
2016-02-24 15:32:46 -08:00
Howard Mao
8a877fa620
Add Matthew Naylor's trace generator and AXE scripts
2016-02-24 14:39:11 -08:00
Howard Mao
8c02cb09ca
some additions to Travis and fixes for Testing
2016-02-23 23:37:29 -08:00
Palmer Dabbelt
90a73c621d
Merge pull request #58 from ucb-bar/more-travis-fixing
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More travis fixing
2016-02-23 21:26:16 -08:00
Palmer Dabbelt
58d6af207f
Cache all the Scala build directories
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I hope this will result in Travis building our stuff a lot faster, since this
currently takes about half the time.
2016-02-23 16:47:48 -08:00
Palmer Dabbelt
c263c636b3
Actually reference all the tests from RISCV
2016-02-23 16:05:27 -08:00
Palmer Dabbelt
ad62afd9ca
Add zscale to regression submodule list
2016-02-23 12:58:08 -08:00
Palmer Dabbelt
700d756de0
Merge pull request #55 from ucb-bar/travis-regression
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travis-ci.org improvements
2016-02-23 12:19:59 -08:00
Palmer Dabbelt
bae4c0c0c9
Point Testing to $RISCV/... not $base_dir/...
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This uses the compiled tests in RISCV, which match the rest of the toolchain.
2016-02-23 10:58:51 -08:00
Colin Schmidt
1e49eb4958
format .travis.yml (trigger rebuilt to test cache)
2016-02-23 10:58:51 -08:00
Colin Schmidt
e097cdcef8
bump tools for install tests fix
2016-02-23 10:58:51 -08:00
Palmer Dabbelt
28c91795c3
Enable travis caching
2016-02-23 10:58:51 -08:00
Palmer Dabbelt
edd0b3b824
Move travis to the regression Makefile
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We want to add support for caching riscv-tools builds on Travis and the easiest
way to do so looks like to jus go ahead and use
2016-02-23 10:58:51 -08:00
Palmer Dabbelt
0ac5c07683
Merge pull request #54 from ucb-bar/fsim-no-htif
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The FPGA doesn't have an HTIF clock divider
2016-02-22 20:02:03 -08:00
Palmer Dabbelt
a073c37e36
The FPGA doesn't have an HTIF clock divider
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We used to just be writing the SCR anyway, but now that the SCR maps are
automatically defined VCS will detect the missing SCR and bail out when
compiling test harness code. This patch just doesn't write the HTIF SCR when
there isn't one.
2016-02-22 16:15:07 -08:00
Colin Schmidt
c1b5f71ee7
don't run bmarks in parallel
2016-02-22 13:34:24 -08:00
Colin Schmidt
4ce603e548
Memtest configs should not have a hex file loaded
2016-02-22 12:49:26 -08:00
Colin Schmidt
43c2237ef7
add more memtest configs and remove channel test
2016-02-22 09:38:44 -08:00
Colin Schmidt
0c575403af
only use a single asm test and 1 bmark for memtest
2016-02-22 09:36:53 -08:00
Colin Schmidt
e4c4a90648
add a config to travis for memchannel mux select
2016-02-22 09:36:53 -08:00
Colin Schmidt
3dae576c9e
add travis configs for memtest
2016-02-22 09:36:53 -08:00
Howard Mao
4fedd180ee
bump uncore and groundtest
2016-02-19 23:31:09 -08:00
Howard Mao
85cc632d5d
fix emulator debug build
2016-02-19 23:13:57 -08:00
Howard Mao
5e4a02038c
move FPGA AXI to HTIF converter into Chisel module
2016-02-19 13:53:31 -08:00
Palmer Dabbelt
926efd0cab
Allow the number of memory channels to be picked at runtime
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We're building a chip with 8 memory channels. Since this will require a
complicated test setup we want to also be able to bring up the chip with fewer
memory channels. This commit adds a SCR that controls the number of active
memory channels on a chip. Toggling this SCR will scramble memory and drop
Nasti messages, so it's only possible to change while the chip is booting.
By default this just adds a 1-bit SCR, which essentially no extra logic.
When multiple memory channel configurations are enabled at elaboration time, a
NastiMemoryInterconnect is generated for each channel configuration. The
number of outstanding misses is increased to coorespond to the maximum number
of banks per memory channel (added as a parameter), which I believe is
necessary to avoid deadlock in the memory system.
A configuration is added that supports 8 memory channels but has only 1 enabled
by default.
2016-02-17 15:23:30 -08:00
Palmer Dabbelt
95b065153d
Add CDE to the submodule list
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Without this I don't get rebuilds when toching a file in CDE.
2016-02-17 15:23:25 -08:00
Palmer Dabbelt
db9de94588
Generate and use SCR address header files
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This uses the new SCRFile changes to generate a header file containing a list
of all the SCRs in a core to remove the magic constant "63" (the HTIF clock
divider control register) and replace it with a generated number (which is
still 63).
2016-02-17 15:23:18 -08:00
Christopher Celio
8687ce5ebd
bump torture
2016-02-16 15:13:59 -08:00
Christopher Celio
2e15d92d18
bump torture
2016-02-16 14:24:31 -08:00
Christopher Celio
c1b4d9372f
Revert "add new parameters for new SCR file"
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This reverts commit 4dad5b8b32
.
The commit breaks the build.
2016-02-13 04:02:20 -08:00
Christopher Celio
6c6bbca92a
Revert "use singleton for global"
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This reverts commit 4d0f941de3
.
The commit breaks the build.
2016-02-13 03:56:47 -08:00
John Wright
4d0f941de3
use singleton for global
2016-02-13 00:56:11 -08:00
John Wright
4dad5b8b32
add new parameters for new SCR file
2016-02-12 18:24:12 -08:00
Howard Mao
9fb2216548
get rid of unused external mmio port
2016-02-10 21:49:02 -08:00
Howard Mao
4b95374f0c
bump rocket for bug fixes
2016-02-10 11:12:48 -08:00
Howard Mao
72a876bfba
add NASTI to TL converter
2016-02-10 11:12:39 -08:00
Palmer Dabbelt
96b77f399c
Merge pull request #43 from ucb-bar/chisel3
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Bump junctions, for a chisel3 fix
2016-02-08 14:42:06 -08:00
Palmer Dabbelt
98baf401a6
Bump junctions, for a chisel3 fix
2016-02-08 13:33:05 -08:00
Andrew Waterman
70945953a8
Merge pull request #42 from ucb-bar/chisel3
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Chisel 3 support
2016-02-05 16:01:35 -08:00
Palmer Dabbelt
b2ed35e8aa
Print a better error on missing config classes
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Without this you don't actually see what config class you tried to use, which
makes it hard to grep around Makefiles to see why things are broken.
2016-02-05 09:59:02 -08:00
Palmer Dabbelt
8422aaf6fc
Add a "/" when targetDir doesn't have one
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This isn't Chisel 3 specific, but that's what I happened to do in the Chisel 3
Driver wrapper.
2016-02-05 09:57:47 -08:00
Palmer Dabbelt
3bb0f11e6c
Chisel3 <> reverse fix
2016-02-05 09:56:42 -08:00
Colin Schmidt
c944193e16
add dma configs to travis
2016-02-02 16:06:01 -08:00
Howard Mao
06c3f9b655
Rocket Chip fixes in response to lowRISC team's comments
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* DMA frontend-backend communication tunneled over TileLink/AXI
* Split MMIO and Mem requests in l1tol2net instead of in AXI interconnect
* Don't make NIOMSHRs configurable. Fixed at 1.
* Connect accelerator-internal CSRs into the CSR file
* Make mtvec register configurable and writeable
2016-02-02 13:14:52 -08:00
Palmer Dabbelt
97640f099d
Merge pull request #41 from ucb-bar/regressions
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Support torture regressions
2016-02-01 18:39:28 -08:00
Palmer Dabbelt
5cea4edee2
Bump riscv-tools for torture NaN ISA change
2016-01-31 23:06:59 -08:00
Palmer Dabbelt
e18759642f
Avoid running Chisel in parallel in the same directory
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It looks like Chisel fails when I try to run it in parallel. This adds a lock
file to ensure that only a single Chisel instance is running at a time when
running the regressions.
2016-01-31 23:06:59 -08:00
Palmer Dabbelt
00465b15c3
Allow the regression Makefile to clean all targets
2016-01-31 23:06:59 -08:00
Palmer Dabbelt
c9a2b7d109
Add torture as part of the regression
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Since the latest Spike fix my torture runs are succeeding, so I can now run it
as part of the regression flow.
2016-01-31 23:06:59 -08:00