Andrew Waterman
a454edaaf7
Treat exceptions as steps for the purposes of single-stepping
2017-04-17 10:28:33 -07:00
Megan Wachs
9cf86fa105
debug: checkpoint pointing to riscv-tools that picks up some tweaks in the debug riscv-tests
2017-04-17 10:28:33 -07:00
Megan Wachs
9a6e7afc93
debug: bump OpenOCD to latest version of newprogram (with Examined RISC-V core message)
2017-04-17 10:28:33 -07:00
Megan Wachs
af6b2d8051
debug: DATA Region has to be aligned for ld/sd to correctly detect 64-bit cores.
2017-04-17 10:28:33 -07:00
Megan Wachs
b44d5f9386
debug: correctly consider .transfer bit in COMMAND
2017-04-17 10:28:33 -07:00
Megan Wachs
79477fbea6
debug: Properly consider 'transfer' bit
2017-04-17 10:28:33 -07:00
Megan Wachs
2dc4be6294
debug: remove preexec. Simplify the state machine since you can always just 'execute' once.
2017-04-17 10:28:33 -07:00
Megan Wachs
c5cb8b714f
debug: Bump version and location of OpenOCD to pick up fix for off-by-1 in hartsel
2017-04-17 10:28:33 -07:00
Wesley W. Terpstra
db5d0737f0
Merge pull request #682 from ucb-bar/jchang
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Add hooks to print debug information into the graphml file
2017-04-14 19:35:17 -07:00
Wesley W. Terpstra
7b8af96fc2
diplomacy: use circles for nodes again
2017-04-14 18:09:14 -07:00
Wesley W. Terpstra
2f22fca615
rocket: reverse input edge for better output
2017-04-14 18:09:14 -07:00
Wesley W. Terpstra
ae8fd0c60f
graphML: don't draw unconnected LazyModules
2017-04-14 18:09:14 -07:00
Wesley W. Terpstra
fcf774f125
graphML: reverse interrupt arrows
2017-04-14 18:09:14 -07:00
Jacob Chang
d3925f0998
Add hooks to print debug information into the graphml file
2017-04-14 18:09:14 -07:00
Wesley W. Terpstra
153178ac4f
Merge pull request #678 from ucb-bar/rammodel-atomics
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RAMModel atomics
2017-04-14 18:08:33 -07:00
Wesley W. Terpstra
ba8be17c9a
tilelink2: RAMModel, use CRC16 to check AMO response
2017-04-14 15:13:40 -07:00
Wesley W. Terpstra
6aeec673f2
util: add a CRC calculator
2017-04-14 15:13:40 -07:00
Wesley W. Terpstra
d794218ec3
tilelink2: RAMModel now checks atomic results
2017-04-14 15:13:40 -07:00
Wesley W. Terpstra
4f0ae1eab7
tilelink2: annotate which test generates RAMModel output
2017-04-14 15:13:40 -07:00
Wesley W. Terpstra
0b65fe9532
unittest: put AtomicAutomata under regression
2017-04-14 15:13:39 -07:00
Wesley W. Terpstra
248acbd1b4
tilelink2: add a generic TL2 atomic evaulation unit
2017-04-14 15:13:39 -07:00
Megan Wachs
fd7f4a4c0f
jtag: make it easier to assign MFR ID externally
2017-04-14 01:03:11 -07:00
Andrew Waterman
34d45b4fb0
Fix whitespace error
2017-04-14 01:03:11 -07:00
Andrew Waterman
fdfcffb0b2
Catch bad physical address MSBs when VA size > PA size
2017-04-14 01:03:11 -07:00
Andrew Waterman
6fbbccca3e
Improve Seq indexing QoR
2017-04-14 01:03:11 -07:00
Andrew Waterman
d203c4c654
Check AMO operation legality in TLB
2017-04-14 01:03:11 -07:00
Yunsup Lee
6359ff96e5
Several ScratchpadSlavePort bug fixes ( #676 )
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* only replicate scratch slave d-channel resp when AMO req
* dtim: port can't support put partial mask with holes
* dtim: use \!isRead instead of isAMO
* Fix ScratchpadSlavePort looking at wrong Acquire message
Rename acq to a in the helper method.
Delete isRead and isWrite altogether.
2017-04-13 23:25:51 -07:00
Andrew Waterman
b9e042d2bf
Unconditionally write badaddr, possibly to zero
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59d33f6b83
2017-04-12 13:35:02 -07:00
Megan Wachs
bef88c4c30
Add pointers to package dependencies to README ( #670 )
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Tell people where to look to find package dependency information
2017-04-11 19:54:46 -07:00
Jim Lawson
907d369bde
Remove tests obsoleted by new FP encoding proposal ( #672 )
2017-04-11 19:12:35 -07:00
Wesley W. Terpstra
37c9ab3459
Merge pull request #671 from ucb-bar/cork-it
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Add a few diplomacy restrictions
2017-04-11 15:55:37 -07:00
Wesley W. Terpstra
1c36ab8bf7
Fragmenter: forbid multiple sink IDs
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Otherwise a slave might respond with different IDs for different
requests and the Fragmenter would violate the requirement that
control signals remain unchanged for a burst.
2017-04-11 12:38:00 -07:00
Wesley W. Terpstra
84dc2ae822
CacheCork: remove probe support
2017-04-11 12:34:18 -07:00
Andrew Waterman
9a983c12a3
Implement new FP encoding proposal
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https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/_r7hBlzsEd8/cWPyJKMzCQAJ
2017-04-10 22:38:25 -07:00
Andrew Waterman
470c6711a7
Do some CSE by hand, per @terpstra
2017-04-10 22:38:25 -07:00
Wesley W. Terpstra
71bf929505
maskgen: support wider granularity result ( #665 )
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Sometimes it is useful to generate a mask with bits that correspond
to a larger unit than bytes.
2017-04-09 20:06:23 -07:00
Andrew Waterman
a43bf2feae
Add vectored interrupt support
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4dcaa944baba6d88466a
2017-04-08 00:29:45 -07:00
Megan Wachs
051acee76c
Debug: Fix off-by-1 for detecting nonexistent harts.
2017-04-07 16:47:16 -07:00
Megan Wachs
01372e1686
use Wire() correctly to assign a value
2017-04-07 16:47:16 -07:00
Megan Wachs
9ae4838708
jtag: Get rid of chisel deprecation warnings
2017-04-07 16:47:16 -07:00
Megan Wachs
22c6f728c3
debug: Use flags for resume instead of program buffer. Untested.
2017-04-07 16:47:16 -07:00
Megan Wachs
d361e9e343
debug: temporarily leave preexec in place
2017-04-07 16:47:16 -07:00
Megan Wachs
0e2c34b0d6
debug: update register map with new spec
2017-04-07 16:47:16 -07:00
Megan Wachs
df5caba7bf
debug: Make it easier to override parts of the Default Debug Config ( #655 )
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* Handle single-step with a pipeline stall, not a flush
The pipeline flush approach broke when I changed the pipeline stage
the flush happens from
* debug: Make it easier to override parts of the Default Debug Config
* Fix typo in Debug code generation
abstractGeneratedI should be abstractGeneratedS when pulling out the opcode.
This doesn't actually break anything, but fix it for clarity.
2017-04-06 10:33:17 -07:00
Andrew Waterman
5c458322b5
bump chisel for withReset bugfix
2017-04-05 21:46:55 -07:00
Andrew Waterman
c861c4925e
Don't signal access exceptions on invalid PTEs
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The PPN should not be interpreted in this case.
2017-04-05 21:46:55 -07:00
Andrew Waterman
2e09253d26
Revive I$ parity option
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Pipeline the parity check into the second stage, so that the data
RAM access + parity check do not become the critical path.
2017-04-05 21:46:55 -07:00
Andrew Waterman
43917dd59f
Get I$ s1_kill signal off the critical path
2017-04-05 21:46:55 -07:00
Andrew Waterman
744fb2e4b9
Cut imem.resp.ready critical path with a flow queue
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This is only necessary for RVC, where the decode latency is much higher.
2017-04-05 21:46:55 -07:00
Andrew Waterman
3e72f9779f
Handle single-step with a pipeline stall, not a flush
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The pipeline flush approach broke when I changed the pipeline stage
the flush happens from
2017-04-05 19:52:44 -07:00
