riscv/rocket-chip
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Author SHA1 Message Date
Andrew Waterman 6e540825b2 Use entire 12-bit CSR address 2015-03-14 02:15:24 -07:00
Andrew Waterman d04da83f96 Make data RAMs 1RW instead of 1R1W 2014-12-15 17:36:17 -08:00
Andrew Waterman 9bf10ae5d2 remove extraneous toBits (need new Chisel) 2013-09-19 15:26:36 -07:00
Andrew Waterman cc7783404d Add memory command M_XA_XOR 2013-09-12 16:09:53 -07:00
Andrew Waterman 0672773c1a for now, don't use asserts outside of components 2013-05-09 02:14:44 -07:00
Andrew Waterman 7ff5b5b86f treat load-reserved as a non-dirtying store 2013-04-07 19:25:26 -07:00
Andrew Waterman 3479f1c6cd add LR/SC support 2013-04-07 19:25:20 -07:00
Andrew Waterman 944f56a766 remove duplicate definitions 2013-02-28 14:55:19 -08:00
Andrew Waterman 1945fa898b make external clock divider programmable 2013-01-24 23:40:47 -08:00
Andrew Waterman 62a3ea4113 fix some LLC bugs 2012-07-11 17:56:39 -07:00
Andrew Waterman 0aa33bf909 fix some LLC bugs 2012-07-11 17:56:39 -07:00
Andrew Waterman 1ebfeeca8a add L2$ 
It still has performance bugs but no correctness bugs AFAIK.
 2012-07-10 05:23:29 -07:00
Andrew Waterman 66cf690261 add L2$ 
It still has performance bugs but no correctness bugs AFAIK.
 2012-07-10 05:23:29 -07:00