Andrew Waterman
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a5a020f97b
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update chisel and remove SRAM_READ_LATENCY
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2012-01-23 20:59:38 -08:00 |
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Henry Cook
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8766438bb9
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Updated chisel removes ^^ from language. Removed from rocket source, updated jar.
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2012-01-23 17:09:23 -08:00 |
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Andrew Waterman
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e7bf07d55e
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fix AMO replay bug
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2012-01-23 15:35:53 -08:00 |
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Andrew Waterman
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31c56228e2
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add missing "otherwise"
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2012-01-21 20:13:15 -08:00 |
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Henry Cook
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97f0852b17
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DM cache with assoc-aware subunits passes all asm and bmarks
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2012-01-18 17:53:26 -08:00 |
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Henry Cook
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8623d58724
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split into two caches, compiles
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2012-01-18 17:09:35 -08:00 |
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Henry Cook
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7e25749581
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Groundwork for assoc cache implementation
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2012-01-18 17:09:35 -08:00 |
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Henry Cook
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1d76255dc1
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new chisel version jar and find and replace INPUT and OUTPUT
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2012-01-18 14:39:57 -08:00 |
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Andrew Waterman
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addfe55735
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add FPGA memory generator script
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2012-01-13 18:19:08 -08:00 |
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Andrew Waterman
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938b142d64
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require writes to memory to be uninterrupted
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2012-01-03 18:41:53 -08:00 |
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Andrew Waterman
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ffe23a1ee8
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fix WAW hazard handling
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2012-01-02 00:25:11 -08:00 |
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Andrew Waterman
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f9160c53cf
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fixes for correct verilog generation
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2011-12-29 23:46:21 -08:00 |
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Andrew Waterman
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d65e1a2eee
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vlsi verilog compiles now but doesn't simulate
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2011-12-20 22:08:27 -08:00 |
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Andrew Waterman
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a8d0cd95e6
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hellacache now works
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2011-12-17 03:26:11 -08:00 |
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Andrew Waterman
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56c4f44c2a
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hellacache returns!
but AMOs are unimplemented.
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2011-12-12 06:49:39 -08:00 |
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Andrew Waterman
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8308345364
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work in progress on hellacache
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2011-12-10 07:01:47 -08:00 |
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Andrew Waterman
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ce201559f3
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Support cache->cpu nacks one cycle after request
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2011-12-10 00:42:09 -08:00 |
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Andrew Waterman
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c01e1f1cef
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Don't replay from EX stage.
EX replays are now handled from MEM. We may move them to WB.
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2011-12-09 19:42:58 -08:00 |
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