 Wesley W. Terpstra
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5495705acf
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Configs: enable AHB for FPGAs
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2016-06-06 21:36:09 -07:00 |
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Wesley W. Terpstra
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ef27cc3a33
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RocketChip: handle atomics only if needed
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2016-06-06 21:36:03 -07:00 |
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Wesley W. Terpstra
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3e0ec855cf
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RocketChip: add ahb mem interface
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2016-06-06 21:35:59 -07:00 |
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Wesley W. Terpstra
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d2b505f2d2
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RocketChip: rename mem to mem_axi in preparation for new bus type
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2016-06-06 21:35:55 -07:00 |
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Wesley W. Terpstra
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2086c0d603
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Configs: add a parameter to control the memory subsystem interface
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2016-06-06 21:35:43 -07:00 |
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Wesley W. Terpstra
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2ddada1732
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ahb: add mmio_ahb option
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2016-06-06 21:35:39 -07:00 |
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Wesley W. Terpstra
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31f1dcaf84
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ahb: rename mmio outputs to mmio_axi
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2016-06-06 21:35:34 -07:00 |
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Wesley W. Terpstra
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7a24527448
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ahb: make MMIO channels specifiy bus type (we will have more than one bridge)
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2016-06-06 21:35:30 -07:00 |
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Wesley W. Terpstra
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f3a557b67b
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ahb: AHB parameters should be site specific
Conflicts:
src/main/scala/Configs.scala
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2016-06-06 21:35:24 -07:00 |
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Wesley W. Terpstra
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976d4d3184
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ahb: AHB parameters should match TileLink parameters by default
Closes #116
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2016-05-25 18:01:25 -07:00 |
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Wesley W. Terpstra
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da566e7d6a
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build: use local sbt when building firrtl
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2016-05-25 11:48:03 -07:00 |
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