Henry Cook
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9769b2747c
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now depend on external cde library rather than chisel.params (bump all submodules)
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2015-10-21 18:24:16 -07:00 |
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Henry Cook
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c4eadbda57
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Removed all traces of params
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2015-10-06 11:42:06 -07:00 |
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Henry Cook
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51c42083d0
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Add new junctions repo as submodule (contains externally facing buses and peripherals).
Bump all submodules.
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2015-07-29 18:15:45 -07:00 |
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Henry Cook
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bd4ff35a4b
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Upgrade sbt to 0.13.8, simplify build.scala Tasks, generate tests from TestGenerator App, set addons with env variable ROCKETCHIP_ADDONS
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2015-07-22 11:49:10 -07:00 |
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Yunsup Lee
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e7802825c3
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add Zscale testing
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2015-07-17 12:02:02 -07:00 |
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Yunsup Lee
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4c7c3f5bb2
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add test generate for ZscaleTop
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2015-07-14 16:26:28 -07:00 |
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Henry Cook
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302cd3e638
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Added BuildZscale param for use in Top and makefrag generation
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2015-07-13 15:46:42 -07:00 |
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Yunsup Lee
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09e29e8fe0
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add zscale
only supports generating Verilog, which plugs into the fpga-spartan6 repository, for now
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2015-07-07 20:38:47 -07:00 |
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