- Make API more idiomatic (x holdUnless y, instead of holdUnless(x, y))
- Add new SeqMem API, readAndHold, which corresponds to most common
use of holdUnless
* [rocket] Refactor Tile into cake pattern with traits
* [rocket] cacheDataBits &etc in HasCoreParameters
* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters
* [rocket] frontend and icache now diplomatic
* [rocket] file name capitalization
* [rocket] re-add hook for inserting externally-defined Cores
* [rocket] add FPUCoreIO
* [groundtest] move TL1 Config instances to where they are used
* [unittest] remove legacy unit tests
* [groundtest] remove legacy device tests
A lot of utility code was just being imported willy-nilly from one
package to another. This moves the common code into util to make things
more sensible. The code moved were
* The AsyncQueue and AsyncDecoupledCrossing from junctions.
* All of the code in rocket's util.scala
* The BlackBox asynchronous reset registers from uncore.tilelink2
* The implicit definitions from uncore.util
* rocketchip: rename identically names devices with _%d
If you connect two devices with the same name in TL2 (totally ok there),
when they get put into the TL1 addrmap, one gets silently overwritten.
This renames the second occurance as _1, third as _2, and so on...
* junctions: blow if duplicates add to addrmap
* crossing: use async reset
* crossings: asyncqueue needs Asynchronous reset.
* crossing: Actually enable the head of the synchronizer flop chain
* crossing: remove reset from logic. This flop will no longer be written during reset because valid will be low.
* crossing: Tidy up code & comments
Unfortunately, I had to touch a lot of code, which weren't quite possible to split up into multiple commits.
This commit gets rid of the "extra" infrastructure to add periphery devices into Top.
This is a temporary fix, which can generate more hardware than necessary, but this is OK for now, since this code will soon be replaced with tilelink2 code.
