riscv/rocket-chip
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8db2e8829f
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43 Commits

Author SHA1 Message Date
Megan Wachs
8db2e8829f Allow aggregate CONFIG on Command Line 2016-08-01 14:24:16 -07:00
Andrew Waterman
fe670e5421 Stop using deprecated FileSystemUtilities to create files 2016-07-31 18:04:56 -07:00
Andrew Waterman
058396aefe [rocket] Implement RVC 2016-07-29 17:56:42 -07:00
Howard Mao
6a5b2d7f59 fix assembly tests for configurations without VMU and/or user mode 2016-07-22 17:21:57 -07:00
Andrew Waterman
ba08255450 bump rocket 2016-07-14 22:11:19 -07:00
Andrew Waterman
32ee5432dd Fix testing of DefaultSmallConfig; bump rocket et al 2016-07-07 21:23:49 -07:00
Andrew Waterman
568bfa6c50 Purge legacy HTIF things 
The SCR file is gone, too, because it was tightly coupled.  The
general concept could be revived as a module that somehow connects
to the debug module.
 2016-06-23 13:23:57 -07:00
Howard Mao
4fbe7d6cf7 split the isa tests properly 2016-06-22 16:14:02 -07:00
Andrew Waterman
9e86b9efc9 Add provisional breakpoint support 2016-06-08 22:34:19 -07:00
Andrew Waterman
e82c080c3c Add blocking D$ 2016-05-25 11:09:50 -07:00
Howard Mao
f52fc655a5 remove zscale 2016-05-19 09:43:15 -07:00
Colin Schmidt
abb0e2921b return non-zero exit codes when an assertion fires 
This ensures that assertion failures, which currently print a message to
the console but return a successful exit code, now will cause non-zero
exit code. This is meant to help automated tools like travis and
buildbot do a better job at catching assertions.
This impacts the various run-* targets in the simulation
directories.
 2016-05-18 12:57:58 -07:00
Andrew Waterman
aac89ca1f0 Add PLIC 2016-05-10 00:27:31 -07:00
Howard Mao
4045a07eda Remove need for separate riscv-tests for groundtest 2016-05-03 18:29:46 -07:00
Howard Mao
487d0b356e fixes to get groundtest working with priv-1.9 changes 2016-05-03 13:09:44 -07:00
Andrew Waterman
6d1e82bddf Remove mtohost/mfromhost/mipi CSRs; stub out Rocket CSR port 2016-05-02 15:21:55 -07:00
Andrew Waterman
46bbbba5e6 New address map 2016-04-30 20:59:36 -07:00
Howard Mao
c081a36893 Revert "Bump chisel3 and firrtl, add support for firrtl $ delimiter" 
This reverts commit 5378f79b50.
 2016-03-30 19:06:32 -07:00
jackkoenig
5378f79b50 Bump chisel3 and firrtl, add support for firrtl $ delimiter 2016-03-29 20:16:07 -07:00
Andrew Waterman
9dc0cbdfa4 WIP on privileged spec v1.9 2016-03-14 18:03:33 -07:00
Andrew Waterman
25091003af Add RV32 test/configuration options 
These won't actually work until further commits.  Rocket RV32 support
is complete, but on the priv-1.9 branch.
 2016-03-10 17:40:21 -08:00
Colin Schmidt
ef4915bd2c make the asm suites ordered by their insertion order 2016-02-24 19:49:35 -08:00
Colin Schmidt
ad81d95751 add run-asm-{p,pt,v}-tests targets for convenience 2016-02-24 19:49:35 -08:00
Howard Mao
8c02cb09ca some additions to Travis and fixes for Testing 2016-02-23 23:37:29 -08:00
Palmer Dabbelt
c263c636b3 Actually reference all the tests from RISCV 2016-02-23 16:05:27 -08:00
Palmer Dabbelt
bae4c0c0c9 Point Testing to $RISCV/... not $base_dir/... 
This uses the compiled tests in RISCV, which match the rest of the toolchain.
 2016-02-23 10:58:51 -08:00
Colin Schmidt
4ce603e548 Memtest configs should not have a hex file loaded 2016-02-22 12:49:26 -08:00
Palmer Dabbelt
db9de94588 Generate and use SCR address header files 
This uses the new SCRFile changes to generate a header file containing a list
of all the SCRs in a core to remove the magic constant "63" (the HTIF clock
divider control register) and replace it with a generated number (which is
still 63).
 2016-02-17 15:23:18 -08:00
Palmer Dabbelt
b2ed35e8aa Print a better error on missing config classes 
Without this you don't actually see what config class you tried to use, which
makes it hard to grep around Makefiles to see why things are broken.
 2016-02-05 09:59:02 -08:00
Palmer Dabbelt
8422aaf6fc Add a "/" when targetDir doesn't have one 
This isn't Chisel 3 specific, but that's what I happened to do in the Chisel 3
Driver wrapper.
 2016-02-05 09:57:47 -08:00
Andrew Waterman
e25a020e60 Construct device tree ROM in MMIO region 
Rebuild riscv-tools for this to work!
 2015-11-25 21:23:37 -08:00
Howard Mao
dcef020ca0 get multichannel simulation working in emulator 2015-11-05 10:48:32 -08:00
Yunsup Lee
0d245741bc add multichannel NASTI support in Verilog testbench 2015-11-05 10:48:32 -08:00
Colin Schmidt
854feab08e add knob and constraint dumping 2015-10-22 17:25:38 -07:00
Henry Cook
9769b2747c now depend on external cde library rather than chisel.params (bump all submodules) 2015-10-21 18:24:16 -07:00
Christopher Celio
c9d89226fb Generated *.d file of tests now kept in order 
-Changed Set to LinkedHashSet in Testing.scala
 2015-09-11 18:36:04 -07:00
Henry Cook
51c42083d0 Add new junctions repo as submodule (contains externally facing buses and peripherals). 
Bump all submodules.
 2015-07-29 18:15:45 -07:00
Henry Cook
d21ffa4dba Streamline makefiles for more robust test dependency generation. Note: emulator/generated-src-debug no longer used 2015-07-28 00:24:07 -07:00
Yunsup Lee
efd6458a3d add zscale programs 2015-07-27 19:06:06 -07:00
Henry Cook
bd4ff35a4b Upgrade sbt to 0.13.8, simplify build.scala Tasks, generate tests from TestGenerator App, set addons with env variable ROCKETCHIP_ADDONS 2015-07-22 11:49:10 -07:00
Yunsup Lee
a99b1e3a01 append config name to generated Makefrag filename 2015-07-17 12:34:49 -07:00
Henry Cook
76046c52fe Cleanup testing rv64uf 2015-07-13 18:58:58 -07:00
Henry Cook
407d8e473e first cut at parameter-based testing 2015-07-13 14:54:26 -07:00