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Commit Graph

27 Commits

Author SHA1 Message Date
Andrew Waterman
7c9a1b0265 Correctly check for virtual-address canonicalization
The previous check was necessary but not sufficient.
2018-01-02 18:41:25 -08:00
Richard Xia
50de991f18 Fix typo in breakpoint cover property. 2017-12-04 14:04:24 -08:00
Richard Xia
29c70501f2 Add cover properties for exceptions in the core. 2017-11-30 14:27:04 -08:00
Andrew Waterman
4ebca73d59 Provide option to support AMOs only on I/O, not DTIM/D$ 2017-11-09 17:45:53 -08:00
Andrew Waterman
d0c6cbba6b Improve frontend branch prediction
- Put correctness responsibility on Frontend, not IBuf, for improved
  separation of concerns.  Frontend must detect case that the BTB
  predicts a taken branch in the middle of an instruction.

- Pass BTB information down pipeline unconditionally, fixing case that
  screws up the branch history when the BTB misses and the instruction
  is misaligned.

- Remove jumpInFrontend option; it's now unconditional.

- Default to one-bit counters in the BHT.  For tiny BHTs like these, it's
  more resource efficient to have a larger index space than to have
  hysteresis.
2017-11-09 00:00:56 -08:00
Christopher Celio
c4978712c9 csr: allow for superscalar decode (#1069)
* CSR provides a decode port to check for an illegal instruction.
   * This commit now allows for multiple instructions in decode to get this
      illegal instruction information.
   * This commit leverages the existing decodeWidth parameter. This will
      potentially over-provision the number of decode ports needed for
      RVC-enabled cores.

Closes #1068
2017-10-25 13:58:26 -07:00
Andrew Waterman
a0e5a20b60 Don't route branch comparison result through ALU output mux
This potentially mitigates a critical path, and makes the ALU usable
in processors that have dedicated branch comparators.
2017-10-07 17:36:24 -07:00
Andrew Waterman
5cfe070932 Add option to make misa read-only 2017-10-03 17:34:18 -07:00
Andrew Waterman
09468a272b Add option to remove basic counters (mcycle/minstret) 2017-10-03 17:34:18 -07:00
Andrew Waterman
ab0821f25b Move microarchitecture-neutral params from Rocket to Core
This makes some of the units more reusable.
2017-10-03 17:34:18 -07:00
Andrew Waterman
190d5c50d9 Remove deprecated custom-CSR support 2017-10-03 17:34:18 -07:00
Andrew Waterman
9eaf50762e Don't report exceptions as valid instructions in the printed log 2017-09-27 16:29:42 -07:00
Andrew Waterman
31c5246446 Provide correct trace insn on interrupts when possible 2017-09-27 16:27:53 -07:00
Andrew Waterman
026fa14bf8 Rename trace.addr -> iaddr 2017-09-20 14:32:41 -07:00
Andrew Waterman
f1a506476b Merge pull request #994 from freechipsproject/beu
Add L1 bus-error unit
2017-09-20 12:17:08 -07:00
Andrew Waterman
afad25fceb Integrate L1 BusErrorUnit 2017-09-20 00:05:07 -07:00
Andrew Waterman
4d6d6ff641 Add instruction-trace port 2017-09-19 22:59:57 -07:00
Megan Wachs
88332bd885 max-core-cycles: Add a +max-core-cycles PlusArg 2017-08-13 15:47:14 -07:00
Palmer Dabbelt
fc0d5fcf98 Print out the compressed instruction when executing one 2017-08-07 17:21:53 -07:00
Andrew Waterman
b9b4142bb4 Get s2_nack off the critical path
We were using it to compute the next PC on flush vs. replay (which require
PC+4 and PC, respectively).  This fix gets rid of the adder altogether by
reusing the M-stage PC in the flush case, which by construction holds PC+4.
2017-08-05 00:30:36 -07:00
Andrew Waterman
06a831310b Shave a gate delay off I$ backpressure path
The deleted code was a holdover from Hwacha's vector fences.
2017-08-04 13:12:43 -07:00
Andrew Waterman
7d2dd3769f Optimize a hazard check critical path 2017-08-02 14:27:25 -07:00
Andrew Waterman
fdb8935712 Improve fidelity of two perf counters 2017-07-28 13:14:04 -07:00
Andrew Waterman
4c82f6b77e Don't refill BTB on not-taken branches 2017-07-28 13:13:52 -07:00
Andrew Waterman
15878d4691 Perform some control-flow transfers within the Frontend 2017-07-25 15:19:16 -07:00
Andrew Waterman
5df8f0d1ea Add L2 TLB miss counter 2017-07-25 15:19:16 -07:00
Henry Cook
4c595d175c Refactor package hierarchy and remove legacy bus protocol implementations (#845)
* Refactors package hierarchy.

Additionally:
  - Removes legacy ground tests and configs
  - Removes legacy bus protocol implementations
  - Removes NTiles
  - Adds devices package
  - Adds more functions to util package
2017-07-07 10:48:16 -07:00