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riscv/rocket-chip
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Author SHA1 Message Date
Matthew Naylor bda5772e98 Updates to the trace-generator: (1) Don't terminate via HTIF exit, which can cause other, unfinished, cores to be cut short. Instead emit FINISHED messsages allowing an external process to send a SIGTERM to the emulator once all cores have finished. (2) Add some support for greater address variation without having to recompile, disabled by default. (3) Generate atomic, LR/SC, and fence operations by default in addition to plain loads and stores. These changes require newer versions of files in the rocket-chip/scripts directory. I will submit a pull request for those too. 2016-03-18 12:11:11 +00:00
Matthew NaylorandHoward Mao 04be438847 Avoid conflicting assigments to registers in timers. Give priority to start over stop. 2016-03-16 12:54:19 -07:00
Matthew Naylor 1b6871f3d8 Add author, affiliation, and sponsor info to trace-generator files. 2016-02-23 15:30:11 +00:00
Matthew NaylorandHoward Mao e63fc3bb44 Added trace generator 2016-02-22 08:43:34 -08:00
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