riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
5,164 Commits 1 Branch 0 Tags 13 MiB
7a46715cbc
Commit Graph

5164 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Richard Xia
61c39da475 Check for rvc before declaring illegal instruction after an ebreak. 2017-06-16 10:49:36 -07:00
Megan Wachs
d0f8cdd00c Merge pull request #804 from freechipsproject/travis_cache_stages 
travis: attempt to make 2 build stages for cache
 2017-06-16 07:31:56 -07:00
Wesley W. Terpstra
a89c0551b7 travis: use travis_wait again 
Timeouts due to inactivity again :-/
 2017-06-15 23:04:17 -07:00
Megan Wachs
30a3e3ef55 travis: attempt to make 2 build stages for cache 
First stage builds riscv-tools, next stage builds verilator
 2017-06-15 21:31:15 -07:00
Wesley W. Terpstra
93d423d202 diplomacy: optimize IdRange.contains (#798) 
This should make an optimal circuit for a wider class of ranges.
 2017-06-15 15:56:14 -07:00
Shreesha Srinath
4059d9417f GeneratorUtils: support to elaborate a RawModule 2017-06-15 14:33:02 -07:00
Megan Wachs
d316aeb275 Merge pull request #799 from freechipsproject/bump-riscv-tools-start-multiple-harts 
Bump riscv-tools to pick up FESVR which allows starting all harts
 2017-06-15 13:55:46 -07:00
Henry Cook
5368ea60fe Merge pull request #757 from freechipsproject/isp-port 
Inter-System-Port
 2017-06-15 13:07:19 -07:00
Megan Wachs
9a789fc0cf Bump riscv-tools to pick up FESVR which allows starting all harts 2017-06-15 11:05:07 -07:00
Jack Koenig
2665a3eb2f Bump firrtl (#797) 2017-06-15 10:06:24 -07:00
Wesley W. Terpstra
c259e39fa3 Merge pull request #796 from freechipsproject/buffer-instance 
diplomacy: BufferParams can now directly create a Queue
 2017-06-14 15:58:29 -07:00
Wesley W. Terpstra
1f8c4ba4ca CoreplexNetwork: don't force a buffer on the coherence manager 
Let the l2Config.coherenceManager create its own appropriate buffers.
This can matter if you need to make sure the buffer is in the right
place in the hierarchy for hierarchical place and route.
 2017-06-14 14:27:23 -07:00
Wesley W. Terpstra
4a15d47061 diplomacy: BufferParams can now directly create a Queue 2017-06-14 13:47:37 -07:00
Wesley W. Terpstra
36562ce48e Merge pull request #794 from freechipsproject/xbar-debug 
Deal with lots of sources more gracefully.
 2017-06-13 19:44:28 -07:00
Wesley W. Terpstra
c85486e67c travis: don't give up if gcc is slow to build riscv-tools 2017-06-13 16:59:31 -07:00
Wesley W. Terpstra
b4b165112c PeripheryErrorSlave: do not put a TLMonitor between the fragmenter and slave 
This edge has the largest number of source bits by far. Let's just exclude it.
 2017-06-13 16:59:29 -07:00
Wesley W. Terpstra
94f85e8bc8 tilelink2: TLMonitor will not create giant wires 2017-06-13 16:58:22 -07:00
Colin Schmidt
8264c0a77e add a debug print for xbar id mappings 2017-06-13 16:58:21 -07:00
Henry Cook
8278d22fcd Merge pull request #776 from freechipsproject/lazy-raw-module-imp 
Use LazyMultiIOModuleImp to simplify top-level traits
 2017-06-13 15:50:12 -07:00
Henry Cook
80a3278139 travis: travis_wait to 80 2017-06-13 14:24:40 -07:00
Henry Cook
9bbde9767c rocketchip: top-level systems are now multi-IO modules 
Cake pattern only 2 layers instead of 3.
Standardized naming convention.
Comments for periphery mix-ins.
Testharnesses use new periphery helper methods.
 2017-06-13 13:55:45 -07:00
Henry Cook
2e8a40a23f diplomacy: Allow LazyModuleImps to be based on RawModules or MultiIOModules 
And add a MonitorBase class to be connect's return type.
 2017-06-13 13:55:27 -07:00
Andrew Waterman
4a24e9a6c6 Merge pull request #792 from freechipsproject/fix-fdiv 
Fix FPU control bug for div/sqrt
 2017-06-09 18:27:19 -07:00
Andrew Waterman
76af15a6ff Fix FPU control bug for div/sqrt 
I was examining a WB-stage control signal instead of a MEM-stage control
signal.  I refactored the code to group the signals together, so that this
sort of bug is less likely going forward.
 2017-06-09 15:51:06 -07:00
Andrew Waterman
e69badb205 Merge pull request #791 from freechipsproject/tlb 
Fix I$ reset regression
 2017-06-09 15:49:25 -07:00
Andrew Waterman
8552c77972 Fix I$ reset regression FU-357 
Can't rely on s2 TLB response, so mask using s2_valid.
 2017-06-09 00:48:24 -07:00
Jack Koenig
0812f9387d Bump firrtl to get performance bug fixes (#790) 
Other new features include version bumping, _RAND instead of _GEN for
termporary variables used for randomization, and printing the full
runtime.
 2017-06-08 17:39:21 -04:00
Andrew Waterman
5a4daebbcc minNum -> minimumNumber (#766) 2017-06-08 11:12:52 -07:00
Andrew Waterman
8cb250cfe6 Fix FMUL sign, again (#789) 2017-06-08 01:50:00 -07:00
Leway Colin
60c896b48c Typo: is should be if ? (#786) 
Typo: is should be if ?
 2017-06-07 10:40:13 -07:00
Andrew Waterman
d45fc0d670 Merge pull request #785 from freechipsproject/fmul-fix 
Fix FMUL sign of zero
 2017-06-06 00:46:03 -07:00
Megan Wachs
f0a59a81c8 Merge pull request #783 from freechipsproject/plusarg_docstring 
plusarg_reader : Add the ability to add a documentation string.
 2017-06-05 18:21:07 -07:00
Andrew Waterman
07ad9203ff Fix FMUL sign of zero 2017-06-05 17:35:42 -07:00
Megan Wachs
8d2e9a8631 Merge remote-tracking branch 'origin/master' into plusarg_docstring 2017-06-05 17:23:44 -07:00
Wesley W. Terpstra
87a5665e43 axi4: only block writes if SAME master has outstanding reads (#782) 
* axi4: only block writes if SAME master has outstanding reads
* tilelink2: ToAXI4 rename variable
TL uses sources, not IDs like AXI. Keep it less confusing.
* tilelink2: ToAXI4 improve stall circuit delay
Don't bother decoding the AXI ID to compute stall.
 2017-06-05 16:54:00 -07:00
Megan Wachs
7afd5e6070 remove unnecessary whitespace. Fix grammar. 2017-06-05 16:18:57 -07:00
Megan Wachs
8440c4b1c4 plusarg_reader : Add the ability to add a documentation string. 2017-06-05 16:16:52 -07:00
solomatnikov
274d908d98 Changed TLXbar arbitration policy to roundRobin (#781) 2017-06-05 10:20:28 -07:00
Andrew Waterman
efce8f06b8 Merge pull request #769 from freechipsproject/new-div-sqrt 
Incorporate new div/sqrt unit
 2017-06-03 03:58:52 -07:00
Andrew Waterman
16ecbdd5b2 Reduce fanout on critical I$ miss signal 2017-06-02 20:45:50 -07:00
Andrew Waterman
27b143013f Improve ITLB QoR 
- No need to check cacheability
- Remove a gate delay from PMP path
 2017-06-02 20:45:50 -07:00
Andrew Waterman
0ffb2c8baf Simplify and improve QoR of ShiftQueue 2017-06-02 20:44:52 -07:00
Andrew Waterman
8229bdee03 Remove FP unboxing from FMA critical path 2017-06-02 20:44:52 -07:00
Andrew Waterman
7504b47bbe Improve code quality in FP->FP and Int->FP units 2017-06-02 20:44:52 -07:00
Andrew Waterman
84c4ae775f Improve QoR for FP->Int conversions 2017-06-02 20:44:52 -07:00
Andrew Waterman
07968df183 Refactor FP Classify 2017-06-02 20:44:52 -07:00
Andrew Waterman
6ecd58a977 Incorporate new div/sqrt unit 2017-06-02 20:44:15 -07:00
Wesley W. Terpstra
b1917e7915 coreplex: add an ISPPort trait to add cross-connect points 2017-06-02 20:43:23 -07:00
Wesley W. Terpstra
81d372137a coreplex: unconditionally insert a Splitter between tiles and l1tol2 2017-06-02 20:43:21 -07:00
Wesley W. Terpstra
d002cec6ac NodeNumberer: add an adapter to map inter-chip fabrics 2017-06-02 20:42:17 -07:00