6de6f38894
Pipeline D$ exception response into s2
2017-04-18 00:47:58 -07:00
cc9ec1d51a
Send D$ grant acks early; accept release acks early
...
We now need to block the B-channel for a few cycles after a grant to
allow the processor to get at least one request through, preventing
livelock.
2017-04-18 00:47:58 -07:00
728569c717
Reduce access-exception generation critical path
2017-04-18 00:47:58 -07:00
c366007a0d
Tighten PMAs for LR/SC and misaligned accesses
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- LR/SC on cacheable memory only (not even scratchpad)
- No misaligned accesses on regions with get/put-effects
2017-04-18 00:47:58 -07:00
74a7838de0
In TLBPermissions, don't merge regions of different types
2017-04-18 00:47:58 -07:00
7871ec82c4
Guarantee probe forward progress during LR storm
2017-04-18 00:47:58 -07:00
debcbca7de
Make PMP tolerant to PA size << VA size
2017-04-17 10:28:33 -07:00
a454edaaf7
Treat exceptions as steps for the purposes of single-stepping
2017-04-17 10:28:33 -07:00
2f22fca615
rocket: reverse input edge for better output
2017-04-14 18:09:14 -07:00
fdfcffb0b2
Catch bad physical address MSBs when VA size > PA size
2017-04-14 01:03:11 -07:00
6fbbccca3e
Improve Seq indexing QoR
2017-04-14 01:03:11 -07:00
d203c4c654
Check AMO operation legality in TLB
2017-04-14 01:03:11 -07:00
6359ff96e5
Several ScratchpadSlavePort bug fixes ( #676 )
...
* only replicate scratch slave d-channel resp when AMO req
* dtim: port can't support put partial mask with holes
* dtim: use \!isRead instead of isAMO
* Fix ScratchpadSlavePort looking at wrong Acquire message
Rename acq to a in the helper method.
Delete isRead and isWrite altogether.
2017-04-13 23:25:51 -07:00
b9e042d2bf
Unconditionally write badaddr, possibly to zero
...
59d33f6b83
2017-04-12 13:35:02 -07:00
470c6711a7
Do some CSE by hand, per @terpstra
2017-04-10 22:38:25 -07:00
a43bf2feae
Add vectored interrupt support
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4dcaa944baba6d88466a
2017-04-08 00:29:45 -07:00
c861c4925e
Don't signal access exceptions on invalid PTEs
...
The PPN should not be interpreted in this case.
2017-04-05 21:46:55 -07:00
2e09253d26
Revive I$ parity option
...
Pipeline the parity check into the second stage, so that the data
RAM access + parity check do not become the critical path.
2017-04-05 21:46:55 -07:00
43917dd59f
Get I$ s1_kill signal off the critical path
2017-04-05 21:46:55 -07:00
744fb2e4b9
Cut imem.resp.ready critical path with a flow queue
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This is only necessary for RVC, where the decode latency is much higher.
2017-04-05 21:46:55 -07:00
3e72f9779f
Handle single-step with a pipeline stall, not a flush
...
The pipeline flush approach broke when I changed the pipeline stage
the flush happens from
2017-04-05 19:52:44 -07:00
127f121ef2
Preserve id_do_fence ( #651 )
2017-04-05 08:29:45 -07:00
19f0ae64a0
Only set id_reg_fence when AMO/FENCE is actually executed
...
This is a performance bug, not a correctness bug. But randomly stalling
because of garbage bits coming out of the I$ should be avoided.
h/t @solomatnikov
2017-04-03 21:13:52 -07:00
410e9cf736
I$ bugfix, to be reworked
2017-03-31 12:17:41 -07:00
b9550e8523
Merge branch 'master' into name-rams
2017-03-30 17:36:01 -07:00
a8a2ee711c
Give I$ RAMs consistent names
2017-03-30 15:50:54 -07:00
2720095b8e
Give D$ RAMs consistent names
2017-03-30 15:49:14 -07:00
70e7e90c02
Remove splitMetadata option from L1 caches
...
This is a property of the specific cache microarchitecture, not actually
an independently tunable knob.
2017-03-30 15:48:55 -07:00
9de06f8c83
Merge remote-tracking branch 'origin/master' into debug_v013_pr
2017-03-30 08:01:11 -07:00
fd39eadcd6
New PMP encoding
2017-03-30 00:36:23 -07:00
2f2b472098
rocket: split the interrupt controller into its own node
2017-03-30 00:36:23 -07:00
3546c8d133
If any PMPs are supported, all CSRs exist
2017-03-30 00:36:23 -07:00
8f73a58d90
Report access exception, not page fault, if page-table walk fails
2017-03-30 00:36:23 -07:00
25232070ec
Don't redundantly set resp_ae in PTW
2017-03-30 00:36:23 -07:00
d3bc99e253
get local interrupts out of the tile
2017-03-30 00:36:23 -07:00
0b9fc94421
Assertion for back-to-back uncached and cached ops ( #631 )
2017-03-29 23:07:17 -07:00
d8033b20fc
Merge remote-tracking branch 'origin/master' into debug_v013_pr
2017-03-29 14:58:04 -07:00
44fb3be7d0
Fix MMIO/cache refill concurrency bug in DCache
...
There's a structural hazard on s2_req, so disallow cache refill initiation
while any MMIO loads are in flight.
2017-03-28 17:16:29 -07:00
4215f480ef
Write instruction to badaddr on illegal instruction traps
2017-03-28 00:56:14 -07:00
bb64c92906
csr: Bring functionality in line with v13 spec. ebreak does not cause exception in Debug Mode, it just starts at Debug ROM again.
2017-03-27 21:21:48 -07:00
05cbdced78
Work around zero-entry vec issue in Chisel
2017-03-27 17:57:26 -07:00
d42d8aaea7
Make SEIP writable
2017-03-27 16:37:09 -07:00
c7c357e716
Add local interrupts to core (but not yet to coreplex)
2017-03-27 16:37:09 -07:00
069858a20c
rocket: separate page faults from physical memory access exceptions
2017-03-27 16:37:09 -07:00
ea0714bfcb
rocket: hard-wire UXL/SXL fields to 0
...
a2a3346e73
2017-03-27 16:37:09 -07:00
75eba294ec
DCache: Release from the correct ID as well
2017-03-27 16:30:46 -07:00
4959771c97
Revert "For D$, use source 0 through N-1 for MMIO, not 1 through N"
...
This reverts commit 0538dc77ce
2017-03-27 16:30:46 -07:00
fa7ead6357
Revert "Use Reg(Vec) instead of Seq(Reg) for DCache MMIO"
...
This reverts commit fb6498f2c3
2017-03-27 16:30:46 -07:00
08c4f7cea6
RocketTile: Create a wrapper for SyncRocketTile as well ( #616 )
...
* RocketTile: Create a wrapper for SyncRocketTile as well
There is no guarantee that debugInterrupt is synchronous
to tlClk, even though it is true in the current implementation.
It will not be true in future implementations, as decoupling
this allows the debugInterrupt to be asserted across tlClk
gating/reset scenarios.
Therefore, even for SyncRocketTile, the debug interrupt needs to be
synchronized to coreClk, and for RationalRocketTile, 1 cycle
of synchronization is not sufficient.
Even though other interrupts may be synchronized, we just
synchronize them all to simplify the code at the expense of
a few cycles latency.
It could still be nice to use a parameter vs hard coding "3".
* RocketTile: Actually use the SyncRocketTile wrapper to get properly synchronized resets.
2017-03-27 02:45:37 -07:00
5d1165c850
Express PMP mask generator using a carry chain
...
This allows it to be optimized like an adder, improving QoR when it
is on the critical path.
2017-03-26 14:20:16 -07:00
