16 Commits

Author	SHA1	Message	Date
Christopher Celio	681b43f398	Bug fixes with global history register. ... - Updated in fetch speculatively. * Updates gated off by cpu.resp.fire(). * BTB direction factored into history update. - All branches update the BHT. - Each instruction carries history; index into BHT is recomputed by passing in mem_reg_pc.	2014-09-26 10:39:57 -07:00
Christopher Celio	a71bdbbc54	Update history register in fetch speculatively	2014-09-26 05:42:08 -07:00
Yunsup Lee	8abf62fae3	add LICENSE	2014-09-12 18:06:41 -07:00
Henry Cook	b42a2ab40a	Final parameter refactor	2014-09-01 13:28:58 -07:00
Henry Cook	2de268b3b1	Cache utility traits. Completely compiles, asm tests hang.	2014-08-19 11:38:20 -07:00
Henry Cook	0dac9a7467	Full conversion to params. Compiles but does not elaborate.	2014-08-19 11:38:02 -07:00
Andrew Waterman	88899eafe0	Reduce node count a bit	2014-06-14 13:58:07 -07:00
Andrew Waterman	8bc1c33540	Fix BTB error (requires Chisel update)	2014-05-19 18:56:30 -07:00
Andrew Waterman	cbb37ccc3e	Use Mem instead of Vec[Reg]	2014-05-18 19:25:43 -07:00
Andrew Waterman	4ca152b012	Use BundleWithConf to avoid clone method boilerplate	2014-05-09 19:37:16 -07:00
Andrew Waterman	0c13c00d08	Reduce node count by avoiding elsewhen :-(	2014-05-09 19:30:57 -07:00
Henry Cook	910b3b203a	removed AddressSpaceConstants, CacheConstants, and TileLinkSizeConstants	2014-04-10 12:32:44 -07:00
Andrew Waterman	927287da34	Bypass RAS push/pop	2014-04-07 23:47:53 -07:00
Andrew Waterman	f235fa0db6	Move branch resolution to M stage	2014-04-07 15:58:49 -07:00
Andrew Waterman	db59fc65ab	Add return address stack	2014-04-01 15:01:27 -07:00
Andrew Waterman	e3b12e0b85	Make BTB more complexity-effective ... BTB entries reference a small number of unique pages, so we separate the storage of pages from indices. This makes much larger BTBs feasible. It's easy to exacerbate cycle time this way, so one-hot encoding is used as needed.	2014-03-25 05:22:04 -07:00