66f64a9759
tilelink2 ToAXI4: don't interlock R+W for non-FIFO masters ( #822 )
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idCount <= 1 implies that no more than one transaction can be inflight,
so there is no need to interlock R+W. However, when stripBits > 0, it is
possible for a non-FIFO master to have > 1 idCount. In this case, we
also don't need to interlock R+W.
2017-06-26 17:54:17 -07:00
8ca6c10994
tilelink2: ToAXI4 can strip off low source ID bits
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Some TL converters place extra meta data in the low bits of source.
Examples include the TLFragmenter and CacheCork.
This new argument makes it possible to save AXI4 ID space by reclaiming
those bits upon conversion.
2017-06-23 17:22:45 -07:00
feecfb53ed
axi4: Deinterleaver need not make a Q for an unused AXI id
2017-06-23 17:22:42 -07:00
9bea7c1c58
Merge pull request #815 from freechipsproject/reduce-others
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Reduce others
2017-06-23 12:13:48 -07:00
2d8b2f4edd
ReduceOthers: remove constants from the balanced AND tree
2017-06-23 00:28:05 -07:00
ad4b454b49
isp: passthru based on edgesOut = edgesIn ( #814 )
2017-06-22 21:23:49 -07:00
48611266fa
diplomacy: use ReduceOthers in the RegMapper
2017-06-22 19:43:47 -07:00
11d1cb02eb
util ReduceOthers produces nlogn cost ready-valid logic
2017-06-22 19:43:20 -07:00
1f137cb9ff
Merge pull request #800 from ss2783/patch-1
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GeneratorUtils: support to elaborate a RawModule
2017-06-22 12:34:41 -07:00
aced18b3bb
Move RoCC interface to Diplomacy and TL2 ( #807 )
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* Move RoCC interface to Diplomacy and TL2
* guard rocc arbiter to prevent zero-width wires
2017-06-22 12:07:09 -07:00
bf431c0a53
groundtest: fix test ram width
2017-06-20 18:11:22 -07:00
2f2fe0a973
clint: don't ask for what you know (nTiles)
2017-06-20 17:21:53 -07:00
1c97a2a94c
allow re-positionable PLIC and Clint, and change coreplex internal network names
2017-06-20 17:18:45 -07:00
5552f23294
tims: explictly name them for generated address map
2017-06-20 17:18:29 -07:00
6b79842e66
dcache: just left shift by untagbits to get tag
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Always safe because of the requirement on coreplex/RocketTiles.scala:126
2017-06-20 16:35:28 -07:00
bb309e573f
TLSplitter: special-case the case of no split necessary
2017-06-20 14:10:25 -07:00
53f030c037
TLSplitter: default policy is roundRobin
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Track commit 274d908d98
2017-06-20 14:03:01 -07:00
1aa4f5ce33
TLSplitter: QoR improvements
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Track commit 985d9750e6
2017-06-20 14:01:07 -07:00
f6e0dd12c8
TLSplitter: ManagerUnification is not used in Xbars
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Track the change made in 5994714970
2017-06-20 13:58:30 -07:00
f396b4142d
Merge pull request #806 from freechipsproject/mulh
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Improve integer mul/div
2017-06-20 13:01:16 -07:00
675f183dd2
refactor ICache to be reusable by other frontends ( #808 )
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* refactor ICache to be reusable by other frontends
specifically one that would like to change the fetch width and number of
bytes in an instruction
2017-06-20 08:21:01 -07:00
a6d9884cc0
Improve integer mul/div
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- Signed integer multiplication latency is now deterministic (before,
it would take an extra cycle if the multiplier was negative).
- High-part multiplication is now one cycle faster.
- RV64 MULW now takes half as many cycles as MUL.
- Positive remainders are now one cycle faster.
2017-06-19 12:09:21 -07:00
61c39da475
Check for rvc before declaring illegal instruction after an ebreak.
2017-06-16 10:49:36 -07:00
93d423d202
diplomacy: optimize IdRange.contains ( #798 )
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This should make an optimal circuit for a wider class of ranges.
2017-06-15 15:56:14 -07:00
4059d9417f
GeneratorUtils: support to elaborate a RawModule
2017-06-15 14:33:02 -07:00
5368ea60fe
Merge pull request #757 from freechipsproject/isp-port
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Inter-System-Port
2017-06-15 13:07:19 -07:00
1f8c4ba4ca
CoreplexNetwork: don't force a buffer on the coherence manager
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Let the l2Config.coherenceManager create its own appropriate buffers.
This can matter if you need to make sure the buffer is in the right
place in the hierarchy for hierarchical place and route.
2017-06-14 14:27:23 -07:00
4a15d47061
diplomacy: BufferParams can now directly create a Queue
2017-06-14 13:47:37 -07:00
b4b165112c
PeripheryErrorSlave: do not put a TLMonitor between the fragmenter and slave
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This edge has the largest number of source bits by far. Let's just exclude it.
2017-06-13 16:59:29 -07:00
94f85e8bc8
tilelink2: TLMonitor will not create giant wires
2017-06-13 16:58:22 -07:00
8264c0a77e
add a debug print for xbar id mappings
2017-06-13 16:58:21 -07:00
9bbde9767c
rocketchip: top-level systems are now multi-IO modules
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Cake pattern only 2 layers instead of 3.
Standardized naming convention.
Comments for periphery mix-ins.
Testharnesses use new periphery helper methods.
2017-06-13 13:55:45 -07:00
2e8a40a23f
diplomacy: Allow LazyModuleImps to be based on RawModules or MultiIOModules
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And add a MonitorBase class to be connect's return type.
2017-06-13 13:55:27 -07:00
76af15a6ff
Fix FPU control bug for div/sqrt
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I was examining a WB-stage control signal instead of a MEM-stage control
signal. I refactored the code to group the signals together, so that this
sort of bug is less likely going forward.
2017-06-09 15:51:06 -07:00
8552c77972
Fix I$ reset regression FU-357
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Can't rely on s2 TLB response, so mask using s2_valid.
2017-06-09 00:48:24 -07:00
5a4daebbcc
minNum -> minimumNumber ( #766 )
2017-06-08 11:12:52 -07:00
8cb250cfe6
Fix FMUL sign, again ( #789 )
2017-06-08 01:50:00 -07:00
60c896b48c
Typo: is should be if ? ( #786 )
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Typo: is should be if ?
2017-06-07 10:40:13 -07:00
d45fc0d670
Merge pull request #785 from freechipsproject/fmul-fix
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Fix FMUL sign of zero
2017-06-06 00:46:03 -07:00
07ad9203ff
Fix FMUL sign of zero
2017-06-05 17:35:42 -07:00
8d2e9a8631
Merge remote-tracking branch 'origin/master' into plusarg_docstring
2017-06-05 17:23:44 -07:00
87a5665e43
axi4: only block writes if SAME master has outstanding reads ( #782 )
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* axi4: only block writes if SAME master has outstanding reads
* tilelink2: ToAXI4 rename variable
TL uses sources, not IDs like AXI. Keep it less confusing.
* tilelink2: ToAXI4 improve stall circuit delay
Don't bother decoding the AXI ID to compute stall.
2017-06-05 16:54:00 -07:00
7afd5e6070
remove unnecessary whitespace. Fix grammar.
2017-06-05 16:18:57 -07:00
8440c4b1c4
plusarg_reader : Add the ability to add a documentation string.
2017-06-05 16:16:52 -07:00
274d908d98
Changed TLXbar arbitration policy to roundRobin ( #781 )
2017-06-05 10:20:28 -07:00
16ecbdd5b2
Reduce fanout on critical I$ miss signal
2017-06-02 20:45:50 -07:00
27b143013f
Improve ITLB QoR
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- No need to check cacheability
- Remove a gate delay from PMP path
2017-06-02 20:45:50 -07:00
0ffb2c8baf
Simplify and improve QoR of ShiftQueue
2017-06-02 20:44:52 -07:00
8229bdee03
Remove FP unboxing from FMA critical path
2017-06-02 20:44:52 -07:00
7504b47bbe
Improve code quality in FP->FP and Int->FP units
2017-06-02 20:44:52 -07:00