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4424 Commits

Author SHA1 Message Date
Wesley W. Terpstra 641a4d577a tilelink2: Error device for returning errors on demand 2017-05-01 22:53:02 -07:00
Wesley W. Terpstra a580b17ece axi4: IdIndexer => reduce number of needed ids 2017-05-01 22:53:01 -07:00
Wesley W. Terpstra 06efc01d96 axi4: an adapter to remove user bits 2017-05-01 22:53:01 -07:00
Wesley W. Terpstra f1217519f1 axi4: RegisterRouter; concurrent response illegal in AXI 2017-05-01 22:53:01 -07:00
Wesley W. Terpstra 5163ccd11f axi4: RegisterRouter supports user bits 2017-05-01 22:53:01 -07:00
Wesley W. Terpstra de6ea9b442 axi4: support user bits in SRAM 2017-05-01 22:53:01 -07:00
Wesley W. Terpstra 396ecacda4 AXI4: add an optional user bundle field 2017-05-01 22:53:01 -07:00
Andrew Waterman d6e69066a5 Fix ITIM loads (#716) 
An incorrectly-set ready signal caused bad data to be read from the RAM.
 2017-05-01 17:41:25 -07:00
Andrew Waterman dd85d7e0a0 I$: Don't raise io.resp.valid if io.s1_kill was high previous cycle 
@solomatnikov found the bug.  It doesn't manifest in Rocket because the
Frontend masks io.resp.valid with s2_valid.
 2017-04-28 16:44:58 -07:00
Megan Wachs d67738204f Interrupts: Less Pessimistic Synchronization (#714) 
* interrupts: Less pessimistic synchronization for the different interrupt types. There are some issues with the interrupt number assignments.

* interrupts: Allow an option to NOT synchronize all the external interrupts coming into PLIC

* interrupts: ExampleRocketChipTop uses PeripheryAsyncExtInterrupts. Realized 'abstract' doesn't do what I thought in Scala.

* interrupts: use consistent async/periph/core ordering

* interrupts: Properly condition on 0 External interrupts

* interrupts: CLINT is also synchronous to periph clock
 2017-04-28 14:49:24 -07:00
Andrew Waterman 9b688ce7e2 Merge pull request #707 from ucb-bar/itim 
ITIM
 2017-04-28 02:55:01 -07:00
Andrew Waterman 7416f2a17e Unbreak groundtest 2017-04-28 02:10:33 -07:00
Andrew Waterman 8fd5ecdff8 Set io.cpu.resp.bits.addr for MMIO loads without affecting QoR 2017-04-27 19:50:38 -07:00
Andrew Waterman 7c70aa593e Minor stylistic and QoR improvements to PLIC 2017-04-27 19:35:20 -07:00
Henry Cook 3d0ed80ef6 new parameters ResetVectorBits, MaxHartIdBits, and MaxPriorityLevels 2017-04-27 18:17:31 -07:00
Henry Cook bdb526a9f0 coreplex: DefaultCoreplex => RocketPlex 2017-04-27 18:17:09 -07:00
Andrew Waterman 99de42d34c Swap order of ITIM WidthWidget and Fragmenter 
e99fa057ac accidentally reversed them
 2017-04-27 15:30:02 -07:00
Andrew Waterman 8c10caeef9 Express PMP mask generation with incrementer, not adder 
DC apparently doesn't always pick up the ((x + 1) ^ x) idiom.
Use (x + ~(x + 1)) instead.
 2017-04-27 15:16:29 -07:00
Henry Cook e99fa057ac cleanup scratchpad nodes 2017-04-27 14:02:05 -07:00
Andrew Waterman b2b4725522 Fix zero-width wire issues when ITIM is disabled 2017-04-26 22:43:00 -07:00
Andrew Waterman e23ee274f6 Size hartid field with NTiles, not XLen 2017-04-26 20:11:43 -07:00
Andrew Waterman dc753bfa95 Fix I$ elaboration when ITIM is disabled 2017-04-26 19:35:35 -07:00
Andrew Waterman 80d826b94a Make DTIM deduplicatable 2017-04-26 19:35:35 -07:00
Andrew Waterman 418879a47f Add Instruction Tightly Integrated Memory 2017-04-26 19:35:35 -07:00
Andrew Waterman ee6702e5e0 Support indexing 1-entry Seqs 
It's a zero-width wire special case.

Closes #706.
 2017-04-26 19:35:35 -07:00
Andrew Waterman 2e23d46631 Use val instead of def in ECC calculations 
This allows nicer-looking code to avoid generating lots of redundant nodes.
 2017-04-26 19:35:35 -07:00
Henry Cook 635f119422 Merge pull request #709 from ucb-bar/bump-hardfloat 
bump hardfloat
 2017-04-26 16:47:49 -07:00
Henry Cook ebe27614d2 bump hardfloat 2017-04-26 15:37:29 -07:00
Henry Cook 0a9f632cb0 Merge pull request #708 from ucb-bar/debug_busy_data 
debug: Prevent writes to DATA/PROGBUF when busy
 2017-04-26 14:32:10 -07:00
Megan Wachs 7ad4cc36f7 debug: Prevent writes to DATA/PROGBUF when busy 2017-04-26 11:11:21 -07:00
Megan Wachs e9db531e81 point to riscv-tools README for dependencies (#705) 
As pointed out, if we just point to 'master' branch, then people wouldn't get the correct list of dependencies.
 2017-04-25 20:20:27 -07:00
Henry Cook 1bdb247002 Merge pull request #697 from ucb-bar/async_queue_option 
Add narrowData option to AsyncQueue.
 2017-04-25 17:43:28 -07:00
Henry Cook 7f5f1c7631 Merge branch 'master' into async_queue_option 2017-04-25 14:58:11 -07:00
Henry Cook 95591cc608 Merge pull request #704 from ucb-bar/verbose-require 
Miscellaneous uncore cleanups
 2017-04-25 14:57:58 -07:00
Henry Cook 9bb0d92381 Merge branch 'master' into async_queue_option 2017-04-25 11:23:22 -07:00
Henry Cook 60d71efa36 ahb: make hreadyout fuzzing a sram parameter 2017-04-25 11:11:31 -07:00
Henry Cook ca435c2f40 uncore: more verbose requires 2017-04-25 11:11:31 -07:00
Wesley W. Terpstra f3ab23d068 dcache: fix stupidly wrong crossing comparison (#703) 2017-04-25 09:18:41 -07:00
Wesley W. Terpstra 4807ce7ced dcache: put a flow Q to absorb back-pressure without restarting pipeline (#701) 
* dcache: put a flow Q to absorb back-pressure without restarting pipeline

When used with a RationalCrossing, pipelined MMIO does not come out cleanly.
The first beat works, but if the second beat gets stalled, the pipeline is
restarted. This is a quick hacky test to absorb the beats. Perhaps a better
fix can be made to achieve the same effect.

* dcache: provision as few stages as possible
 2017-04-24 23:28:04 -07:00
Wesley W. Terpstra 9c1d126965 Allow speculative fetch to uncacheable memory if it hits in I$ (#700) 
@aswaterman it's in
 2017-04-24 19:12:37 -07:00
Wesley W. Terpstra 11ff4dfbb9 rocket: seip (int 9) is only present if VM is enabled (#699) 2017-04-24 15:58:33 -07:00
Wesley W. Terpstra d0f3004097 tilelink2: help tools save some registers in the WidthWidget (#691) 2017-04-24 15:13:58 -07:00
Andrew Waterman 65928dc6a0 Don't push RAS for "auipc ra, X; jalr ra, ra, Y" 2017-04-24 02:01:15 -07:00
Andrew Waterman 36a7971975 Bypass scoreboard to reduce MMIO latency 2017-04-24 02:01:15 -07:00
Andrew Waterman 845e6f7458 Filter out duplicate test suites 
I botched the refactoring in 5934c7b4b9
 2017-04-24 02:01:15 -07:00
Andrew Waterman f2d4cb8152 Update RAS speculatively from fetch stage 2017-04-24 02:01:15 -07:00
Andrew Waterman 3b2c15b648 Use tininess-after-rounding in FPU 2017-04-24 02:01:15 -07:00
Andrew Waterman c36c171202 Use correct interrupt priority order 2017-04-24 02:01:15 -07:00
Andrew Waterman bf861293d9 Add ShiftQueue; use it 2017-04-24 02:01:15 -07:00
Andrew Waterman d24d8ff84b Don't stall the frontend, making it easier to add more features later 2017-04-24 02:01:15 -07:00