Rimas Avizienis
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603ede8bfe
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access faults now write badvaddr PCR register with faulting address
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2011-11-10 02:46:09 -08:00 |
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Rimas Avizienis
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36aa4bcc9d
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moved exception handling from ex stage in dpath to mem stage in ctrl
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2011-11-10 02:26:26 -08:00 |
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Rimas Avizienis
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fbfa356d2a
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fixed eret instruction
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2011-11-10 00:37:00 -08:00 |
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Rimas Avizienis
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62407b4668
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more tlb/ptw fixes
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2011-11-10 00:23:29 -08:00 |
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Rimas Avizienis
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c29d2821b4
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cleanup, fixes, initial commit for dtlb.scala
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2011-11-09 21:54:11 -08:00 |
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Rimas Avizienis
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e96430d862
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integrating ITLB & PTW
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2011-11-09 14:52:17 -08:00 |
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Rimas Avizienis
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4d64099103
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cleanup
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2011-11-04 20:52:21 -07:00 |
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Rimas Avizienis
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2db9ee12bc
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fixed eret instruction, hello world runs
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2011-11-04 15:57:08 -07:00 |
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Rimas Avizienis
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4459935554
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dcache fixes - all tests and ubmarks pass, hello world still broken
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2011-11-04 15:40:41 -07:00 |
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Rimas Avizienis
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3a02028a35
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fixes to exception and dcache miss/blocked handling
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2011-11-02 13:32:32 -07:00 |
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Rimas Avizienis
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7a528d6255
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fixes for div/mul hazard checking + cleanup
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2011-11-01 23:14:34 -07:00 |
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Rimas Avizienis
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d8ffecf565
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dcache fix
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2011-11-01 22:10:06 -07:00 |
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Rimas Avizienis
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7479e085ec
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dcache loads working - 1/2 cycle load/use delay depending on load type
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2011-11-01 22:04:45 -07:00 |
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Rimas Avizienis
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3b3d988fde
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dcache loads working - 1/2 cycle load/use delay depending on load type
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2011-11-01 21:25:52 -07:00 |
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Rimas Avizienis
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2b67eee683
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pipeline changes for replay on dcache miss
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2011-11-01 19:05:27 -07:00 |
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Rimas Avizienis
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08b89e7710
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interface cleanup, major pipeline changes
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2011-11-01 17:59:27 -07:00 |
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Rimas Avizienis
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c06e2d16e4
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initial commit of rocket chisel project, riscv assembly tests and benchmarks
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2011-10-25 23:02:47 -07:00 |
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