37a3c22639
rocketchip: move from using cde to config
2016-11-18 16:18:33 -08:00
5bd343bac8
[rocket] d_last && d.fire() => d_done
2016-11-17 18:42:59 -08:00
1ddccb1b33
[rocket] add TODO for single cycle ack
2016-11-17 18:42:59 -08:00
e1992d7c55
[rocket] grant addr bugfix
2016-11-16 18:12:06 -08:00
da7ecfd189
[rocket] probeack vs probeackdata bugfix
2016-11-16 17:27:02 -08:00
1f51564577
[rocket] dcache probe ack data bugfix
2016-11-16 14:25:21 -08:00
66a2c5544e
[rocket] L1D acquire addr bugfix
2016-11-16 13:38:52 -08:00
c5e03c9c76
[rocket] dcache release addr bugfix
2016-11-16 13:14:51 -08:00
0e30364f56
WIP
2016-11-14 13:39:01 -08:00
c0efd247b0
[tl2] expand firstlast api and L1WB bugfix
2016-11-14 12:12:31 -08:00
b7730d66f2
WIP bugfixes: run until corrupted WB data (beats repeated)
2016-11-11 18:34:48 -08:00
71315d5cf5
WIP scala compile and firrtl elaborate; monitor error
2016-11-11 13:07:45 -08:00
afa1a6d549
WIP uncore and rocket changes compile
2016-11-10 15:57:29 -08:00
92ee498521
rocket scratchpad: support atomics
2016-10-31 11:42:47 -07:00
0cc00e7616
regressions: test scratchpad
2016-10-31 11:42:47 -07:00
e9725aea2f
rocketchip: all of the address map now comes from TL2
2016-10-31 11:42:44 -07:00
825c253a72
rocketchip: move TL2 and cake pattern into Coreplex
2016-10-31 11:42:13 -07:00
11121b6f4c
rocket: convert scratchpad to TL2
2016-10-31 11:42:13 -07:00
c22438b822
Fix an overly strict D$ assertion
2016-10-06 15:52:46 -07:00
eddf1679f5
Use <> instead of := for bi-directional connections
2016-10-04 22:29:39 -07:00
7b69f1f261
Don't enter D$ flush state machine if grant outstanding
2016-10-04 14:37:25 -07:00
28beb33943
Make any intervening load/store/fence fail an LR/SC sequence
...
This catches LR/SC misuses more quickly.
2016-10-04 14:37:25 -07:00
b772edcb1b
Allow hit-under-MMIO and multiple MMIOs in blocking D$
...
The latter feature is by default disabled, since there aren't enough
ID bits.
2016-10-01 19:44:05 -07:00
ab3219cf6e
don't use Scala to Chisel implicit conversions outside of rocket
2016-09-29 14:35:42 -07:00
9910c69c67
Move a bunch more things into util package
...
A lot of utility code was just being imported willy-nilly from one
package to another. This moves the common code into util to make things
more sensible. The code moved were
* The AsyncQueue and AsyncDecoupledCrossing from junctions.
* All of the code in rocket's util.scala
* The BlackBox asynchronous reset registers from uncore.tilelink2
* The implicit definitions from uncore.util
2016-09-29 14:23:42 -07:00
5bb575ef74
rename internal/external MMIO network to cbus/pbus respectively
2016-09-21 18:29:28 -07:00
1882241493
move junctions utils into top-level utils package
2016-09-13 20:47:04 -07:00
eaa4b04ee5
Check D$ store->load collisions more precisely
...
Tolerate, for example, a half-word store and a half-word load to
different halves of the same word.
2016-09-09 11:06:42 -07:00
a0dcd42e80
avoid erroneously setting tags valid during flush
2016-09-07 00:05:38 -07:00
63679bb019
Add support for L1 data scratchpads instead of caches
...
They fit in the same part of the address space as DRAM would be, and
are coherent (because they are not cacheable).
They are currently limited to single cores without DRAM. We intend
to lift both restrictions, probably when we add support for
heterogeneous tiles.
2016-09-02 16:22:07 -07:00
7b20609d4d
reorganize moving non-submodule packages into src/main/scala
2016-08-19 13:45:23 -07:00
