riscv/rocket-chip
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785 Commits

Author SHA1 Message Date
Megan Wachs
28eba9b5ac clint/plic: Move the default addresses 2016-10-01 15:46:55 -07:00
mwachs5
9a381e88d1 Suggest sane names for common objects (#369) 
* Suggest sane names for common objects frequently instantiated with factory methods

* Suggest names for common primitives using more Scala-esque Options
 2016-09-30 16:19:25 -07:00
Wesley W. Terpstra
0ebab0976a tilelink2 Isolation: add enable signal (#368) 2016-09-30 04:54:40 -07:00
Wesley W. Terpstra
d3547a6193 tilelink2: Isolation gate insertion module 2016-09-30 01:50:33 -07:00
Wesley W. Terpstra
9b0654be52 tilelink2 Crossing: helpful constructor objects 2016-09-30 01:48:47 -07:00
Wesley W. Terpstra
80f7bb49e3 tilelink2: helper objects operate on OutwardNodes 2016-09-30 01:39:35 -07:00
Howard Mao
4b86802b1a change the configuration interface of SlowIO 2016-09-29 22:16:53 -07:00
Wesley W. Terpstra
6d8c965f04 tilelink2 Crossing: cut the crossing between clock domains 2016-09-29 17:35:10 -07:00
Wesley W. Terpstra
20f42a8762 tilelink2: reuse the halves of the AsyncQueue 2016-09-29 17:35:08 -07:00
Wesley W. Terpstra
8e4c1e567c tilelink2: add types for a TL clockless interface 2016-09-29 17:33:11 -07:00
Wesley W. Terpstra
02ce8c2ca4 tilelink2 Nodes: rename RootNode => BaseNode 2016-09-29 17:33:11 -07:00
Wesley W. Terpstra
754fcf9831 tilelink2: rename BaseNode to SimpleNode 2016-09-29 17:33:11 -07:00
Wesley W. Terpstra
cfdb8ca797 tilelink2 LazyModule: remove obsolete connect method 2016-09-29 17:33:11 -07:00
Wesley W. Terpstra
f2e438833c tilelink2 Nodes: generalize a node into inner and outer halves 
This lets us create nodes which transform from one bus to another.
 2016-09-29 17:33:11 -07:00
Andrew Waterman
2bdf8c2be7 Merge branch 'master' into move-to-util 2016-09-29 14:42:11 -07:00
Howard Mao
ab3219cf6e don't use Scala to Chisel implicit conversions outside of rocket 2016-09-29 14:35:42 -07:00
Howard Mao
9910c69c67 Move a bunch more things into util package 
A lot of utility code was just being imported willy-nilly from one
package to another. This moves the common code into util to make things
more sensible. The code moved were

 * The AsyncQueue and AsyncDecoupledCrossing from junctions.
 * All of the code in rocket's util.scala
 * The BlackBox asynchronous reset registers from uncore.tilelink2
 * The implicit definitions from uncore.util
 2016-09-29 14:23:42 -07:00
Andrew Waterman
e928b741ce Default mtvec=0, not None 
Setting it to None was a mistake.  It makes it far harder to
diagnose boot bugs, as you end up fetching from random addreses
after trapping.
 2016-09-29 13:52:41 -07:00
Megan Wachs
45bd63fcc6 jtag: Prevent Debug RAM accesses from wrapping around, and bring the DTM closer to the Debug Spec 2016-09-29 13:49:14 -07:00
Megan Wachs
449d689a4e jtag: Connect the JTAG DTM side of the synchronizer! 2016-09-29 13:48:55 -07:00
Yunsup Lee
0924f8adb0 print out assigned inerrupt ranges 2016-09-29 11:59:32 -07:00
Yunsup Lee
4c3e8ec1b4 assign interrupt ranges deterministically 2016-09-29 11:59:32 -07:00
Henry Cook
7bca99a27a [tilelink2] Add unit test configs to regression 2016-09-28 18:02:04 -07:00
Henry Cook
32f3f94882 [tilelink2] Fix zero-width wires in RAMModel. 2016-09-28 18:02:04 -07:00
Henry Cook
69e121260e [tilelink2] Add unit tests for many TL2 components 
These tests mostly use the Fuzzer and RAMModel to check that adapters
correctly handle randomly generated legal traffic.
 2016-09-28 18:02:04 -07:00
Henry Cook
81123f84c9 [tilelink2] Make map generation in RRTests a def so that multiple RRTests can be instantiated as part of the same unit test suite. (#356) 2016-09-27 18:06:21 -07:00
Howard Mao
c45cc76cef Get rid of remaining MemIO code 
The only thing we were still using it for was for the MIFDataBits
and MIFTagBits parameters. We replace these with EdgeDataBits and
EdgeIDBits.
 2016-09-27 16:28:17 -07:00
Howard Mao
18e7ea89f2 Get rid of broken groundtests 
The NastiConverterTest, PCIeMockupTest, and DirectGroundtest
configurations have been broken by recent changes.

The NastiConverterTest has been superseded by a unit test and the
other two were only created for an attempt at FPGA debugging.
They weren't actually very useful for that purpose, so might as well get
rid of them.
 2016-09-27 16:28:17 -07:00
Howard Mao
c77c244016 Get rid of NASTI memory interconnects 
These were made for a previous Hurricane tapeout, but we are now doing
all of the memory routing in TileLink, so they are no longer needed.
 2016-09-27 16:28:17 -07:00
mwachs5
f9e0a7ac24 Merge branch 'master' into async_register_crossing 2016-09-27 15:54:34 -07:00
Wesley W. Terpstra
3926cb936b rocketchip: add pbus width and AMO With classes (#357) 2016-09-27 15:52:13 -07:00
Wesley W. Terpstra
eaea138d0d tilelink2: don't use chisel3 namespace (#355) 2016-09-27 14:44:26 -07:00
Henry Cook
f5502df6ab Merge branch 'master' into async_register_crossing 2016-09-27 14:08:27 -07:00
Wesley W. Terpstra
357d06ac9c tilelink2 WidthWidget: Gets must have their mask adjusted (#353) 
The mask of a Get should also be converted.

This manifested as a bug when going from 32=>64 bits. A large Get
could end up with mask that was not full.
 2016-09-27 14:06:02 -07:00
Megan Wachs
3ce08f40a5 crossing: Remove reset from the logic in Register Crossing because it is no longer needed when the underlying crossings are asynchronously reset. Update the order of operations 2016-09-27 13:36:28 -07:00
Howard Mao
71a9c78e4b add WidthAdapter from AXI slave to Coreplex TL slave 2016-09-27 12:48:01 -07:00
Howard Mao
7d6fb950b6 Give TileLink IDs more sensible names 
* Outermost -> MCtoEdge
 * MMIO_Outermost -> MMIOtoEdge

Then the corresponding parameters objects are

 * L1toL2 -> innerParams
 * L2toMC -> outerMemParams
 * L2toMMIO -> outerMMIOParams
 * MCtoEdge -> edgeMemParams
 * MMIOtoEdge -> edgeMMIOParams
 2016-09-27 12:48:01 -07:00
Howard Mao
8a55521b01 move memory width adapter from coreplex to periphery 2016-09-27 12:48:01 -07:00
Howard Mao
e36441a046 use correct parameters object for MMIO width adapter 2016-09-27 12:48:01 -07:00
Howard Mao
201e247f73 Factor coreplex IO connection into separate trait (#350) 
This would allow, for instance, putting the coreplex on a separate clock
domain and crossing the IOs over through asynchronous queues.

The ExampleMultiClockTop* classes are removed since they no longer fit
into the class hierarchy.
 2016-09-27 11:55:32 -07:00
Howard Mao
6316ebd58f make naming of L2toMC parameter object consistent between coreplex and periphery 2016-09-26 17:28:21 -07:00
Howard Mao
ea9f0a868f TileLink utility objects should not take implicit parameters 
We have a handful of TileLink-related helper objects
(wrappers, unwrappers, width adapters, and enqueuers). Previously, using
them could be error-prone, because you had to make sure the implicit
parameters they took in had the same TLId as the TileLinkIO bundles
passed in as inputs. This is rather silly, we should just use the
parameters in the bundle.
 2016-09-26 17:28:21 -07:00
Howard Mao
803739a95c Make sure coreplex mmio's TLId is correct (thanks to zizztux) 2016-09-26 17:28:21 -07:00
Howard Mao
c741ada619 get TraceGen working again 2016-09-26 17:28:21 -07:00
Wesley W. Terpstra
d9e209365d Tl2 addr width0 (#346) 
* tilelink2 Edges: add accessor methods for address and addr_{hi,lo}

* tilelink2: use addr_lo instead of relying on truncation

Truncation can mess up if the width should be 0, but IS 1.
 2016-09-26 17:00:03 -07:00
Wesley W. Terpstra
72c205b54f tilelink2 AddressSet: add .misaligned(low, size) helper method (#345) 
This helps devices with misaligned ranges still connect to TL2.
 2016-09-26 16:01:09 -07:00
Wesley W. Terpstra
dd9558f45d rocketchip: generate GraphML output 2016-09-26 14:35:46 -07:00
Wesley W. Terpstra
1773eb4405 tilelink2 LazyModule: output GraphML of the bus 2016-09-26 14:35:46 -07:00
Wesley W. Terpstra
35da9320bc tilelink2 Nodes: expose connectivity in RootNode 2016-09-26 14:35:46 -07:00
Wesley W. Terpstra
14cd39e045 rocketchip: rename identically names devices with _%d (#340) 
* rocketchip: rename identically names devices with _%d

If you connect two devices with the same name in TL2 (totally ok there),
when they get put into the TL1 addrmap, one gets silently overwritten.
This renames the second occurance as _1, third as _2, and so on...

* junctions: blow if duplicates add to addrmap
 2016-09-26 13:05:49 -07:00
mwachs5
77a0f76289 Cleanup jtag dtm (#342) 
* debug: Clean up Debug TransportModule synchronizer

With async reset async queues, I feel its safe/cleaner
to remove the one-off "AsyncMailbox verilog black-box
and use the common primitive.

I also added some comments about correct usage of this
block. Probably the 'TRST' signal should be renamed
to make it less confusing, as it requires some processing
of the real JTAG 'TRST' signal.
 2016-09-26 11:10:27 -07:00
mwachs5
8641639873 Async rst async queue (#336) 
* crossing: use async reset

* crossings: asyncqueue needs Asynchronous reset.

* crossing: Actually enable the head of the synchronizer flop chain

* crossing: remove reset from logic. This flop will no longer be written during reset because valid will be low.

* crossing: Tidy up code  & comments
 2016-09-26 11:08:38 -07:00
Wesley W. Terpstra
d787bae0d0 tilelink2 Xbar: decouple ready from valid (#338) 
This moves the Xbar from using custom code to using the Arbiter.
The arbiter has better ready-valid decoupling.
 2016-09-23 16:24:29 -07:00
Wesley W. Terpstra
d175bb314d Periphery: make bus width and arithmetic atomics configurable (#337) 2016-09-23 15:25:58 -07:00
Wesley W. Terpstra
47843d8ec1 tilelink2: maxLgSize should be accurate (#332) 2016-09-22 22:06:22 -07:00
Wesley W. Terpstra
c5706afc11 RegField: remove obsolete split method 
This is now natively supported by the regmap(...) invocation.
 2016-09-22 20:52:47 -07:00
Wesley W. Terpstra
fc44151f10 RegField: add name and description fields 
In the future we can generate interesting documentation and headers.
 2016-09-22 20:52:46 -07:00
Wesley W. Terpstra
5e34b313ee RegMapper: regmap(...) now takes BYTE addresses 
If a device has configurable bus-width, we need a stable way of
enumerating registers. The byte offset stays unchanged.

This change also makes it possible to put an arbitrary number of RegFields
starting at some address which are then chopped up into appropriately bus-
sized registers.
 2016-09-22 20:52:46 -07:00
Wesley W. Terpstra
972ca06729 RegField: remove RegField.bytes; it was dangerous 
The implementation unconditionally drove the register.
This made it incompatible with drivers from the device itself.
Besides, writing only parts of a register at a time is ultra-shady.
 2016-09-22 20:52:46 -07:00
Wesley W. Terpstra
a421469754 tilelink2: change adapters to use TLAdapter(params, defaults)(node) 
This API makes it much more readable when you have multiple adapters
combined into a single line. The arguments for each adapter stay
beside the adapter.

For example, this:
  peripheryBus.node := TLWidthWidget(TLBuffer(TLAtomicAutomata()(TLHintHandler(legacy.node))), legacy.tlDataBytes)
becomes this:
  peripheryBus.node := TLWidthWidget(legacy.tlDataBytes)(TLBuffer()(TLAtomicAutomata()(TLHintHandler()(legacy.node))))
 2016-09-22 20:52:46 -07:00
Howard Mao
22053289ef fix typo rv64iu -> rv64ui 2016-09-22 17:33:35 -07:00
Henry Cook
673efb400d Merge branch 'master' into unittest-config 2016-09-22 16:20:53 -07:00
Henry Cook
1e54820f8c Merge remote-tracking branch 'origin/master' into unittest-config 2016-09-22 16:03:51 -07:00
Henry Cook
411ee378de Provide a GeneratorApp object per user package. Extract RocketTestSuite from coreplex into rocketchip and provide GeneratorApp defaults for other target packages. 2016-09-22 15:59:29 -07:00
Henry Cook
391be8d740 tilelink2 RegisterRouter: minLatency is never more than 1 2016-09-22 15:51:15 -07:00
Wesley W. Terpstra
a3e88fa13a tilelink2 Atomics: optimize the sign-extension circuit 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
9f1f6fc61f Comparator: tolerate mismatched data when it is undefined 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
ed038678ef tilelink2 Fuzzer: work around for firrtl/verilator performance issue 
Big Vec()s cause very slow compilation.
 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
1e7480b6fc tilelink2 Monitor: work around for firrtl/verilator performance issue 
Big Vec()s cause problems for these tools.
 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
ec2030df31 tilelink2 Legacy: convert TL1 atomic operand size 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
0a3718881f rocketchip: re-enable testing of atomics 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
e5da3eb8bb tilelink2 Atomics: support arithmetic atomics 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
5b80fe5b51 tilelink2 Atomics: support Logical AMOs 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
4066fbe18f tilelink2 RAMModel: exploit latency to remove bypass 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
e0ade8c5a9 tilelink2 Atomics: exploit minLatency to eliminate bypass 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
3bb2580223 tilelink2 Monitor: detect minLatency violations 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
2b24c4b1b4 tilelink2: most adapters can wipe away latency 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
c115913624 tilelink2 Buffer: increase the minLatency on ports 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
05beb20dc4 tilelink2: specify the minLatency for SRAM+RR 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
44277c1db3 tilelink2 Parameters: include a minLatency parameter for optimization 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
cf39c32b0e tilelink2 Fuzzer: test Atomics 2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
2b9403633d tilelink2 RAMModel: support (by ignoring) atomics 2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
ce204f604a tilelink2 AtomicAutomata: prototype flow control complete 2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
42b10356fa tilelink2: add a general-purpose Arbiter 2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
7636e772c8 tilelink2 Fuzzer: only generate legal atomics 2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
f5d604d8f8 tilelink2 Parameters: poison ports with unsafe atomics 
We need to detect if an AtomicAutomata's output ever gets mixed
with some other source of operations.
 2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
d1151e2f0f tilelink2 Nodes: split connect into eager and lazy halves 2016-09-22 15:18:50 -07:00
Wesley W. Terpstra
684072023f tilelink2 Monitor: make it a LazyModule in the hierarchy 2016-09-22 15:14:20 -07:00
Wesley W. Terpstra
def497861b tilelink2 Bundles: add 1-way snoop bundles 2016-09-22 15:14:20 -07:00
Wesley W. Terpstra
69a1f8cd1f tilelink2 Monitor: detect if sources are mishandled 2016-09-22 15:14:19 -07:00
Henry Cook
83c08a931d [WIP] Generators for unittest and groundtest; disambiguate groundtest.TrafficGenerator 2016-09-22 14:57:18 -07:00
Henry Cook
47c5d1a992 [WIP] Move RocketTestSuite generation into RocketchipGenerator 2016-09-22 14:31:45 -07:00
Albert Ou
d76b762657 tilelink2 Fragmenter: Mask low bits of D channel addr_lo 
This fixes an issue where passing addr_lo through unchanged triggered
unaligned address assertions in the Monitor.
 2016-09-22 12:36:28 -07:00
Howard Mao
cd96a66ba6 replace verilog clock divider with one written in Chisel 2016-09-22 11:32:29 -07:00
Howard Mao
cbd702e48e make sure junctions and uncore unittests both run 2016-09-21 20:17:52 -07:00
Yunsup Lee
1b1ef3be07 simplify base Coreplex bundle 2016-09-21 18:29:28 -07:00
Yunsup Lee
d2df6397cd rename trc (tile reset clock) bundles to tcr (tile clock reset) 2016-09-21 18:29:28 -07:00
Yunsup Lee
5bb575ef74 rename internal/external MMIO network to cbus/pbus respectively 2016-09-21 18:29:28 -07:00
Henry Cook
64fe010369 [unittest] Config import tweaks 2016-09-21 17:40:39 -07:00
Henry Cook
fd5e00fed9 [coreplex] rename Testing.scala -> RocketTestSuite.scala 2016-09-21 17:35:39 -07:00