riscv/rocket-chip
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Author SHA1 Message Date
John Wright
4dad5b8b32 add new parameters for new SCR file 2016-02-12 18:24:12 -08:00
Howard Mao
9fb2216548 get rid of unused external mmio port 2016-02-10 21:49:02 -08:00
Howard Mao
4b95374f0c bump rocket for bug fixes 2016-02-10 11:12:48 -08:00
Howard Mao
72a876bfba add NASTI to TL converter 2016-02-10 11:12:39 -08:00
Palmer Dabbelt
96b77f399c Merge pull request #43 from ucb-bar/chisel3 
Bump junctions, for a chisel3 fix
 2016-02-08 14:42:06 -08:00
Palmer Dabbelt
98baf401a6 Bump junctions, for a chisel3 fix 2016-02-08 13:33:05 -08:00
Andrew Waterman
70945953a8 Merge pull request #42 from ucb-bar/chisel3 
Chisel 3 support
 2016-02-05 16:01:35 -08:00
Palmer Dabbelt
b2ed35e8aa Print a better error on missing config classes 
Without this you don't actually see what config class you tried to use, which
makes it hard to grep around Makefiles to see why things are broken.
 2016-02-05 09:59:02 -08:00
Palmer Dabbelt
8422aaf6fc Add a "/" when targetDir doesn't have one 
This isn't Chisel 3 specific, but that's what I happened to do in the Chisel 3
Driver wrapper.
 2016-02-05 09:57:47 -08:00
Palmer Dabbelt
3bb0f11e6c Chisel3 <> reverse fix 2016-02-05 09:56:42 -08:00
Colin Schmidt
c944193e16 add dma configs to travis 2016-02-02 16:06:01 -08:00
Howard Mao
06c3f9b655 Rocket Chip fixes in response to lowRISC team's comments 
* DMA frontend-backend communication tunneled over TileLink/AXI
 * Split MMIO and Mem requests in l1tol2net instead of in AXI interconnect
 * Don't make NIOMSHRs configurable. Fixed at 1.
 * Connect accelerator-internal CSRs into the CSR file
 * Make mtvec register configurable and writeable
 2016-02-02 13:14:52 -08:00
Palmer Dabbelt
97640f099d Merge pull request #41 from ucb-bar/regressions 
Support torture regressions
 2016-02-01 18:39:28 -08:00
Palmer Dabbelt
5cea4edee2 Bump riscv-tools for torture NaN ISA change 2016-01-31 23:06:59 -08:00
Palmer Dabbelt
e18759642f Avoid running Chisel in parallel in the same directory 
It looks like Chisel fails when I try to run it in parallel.  This adds a lock
file to ensure that only a single Chisel instance is running at a time when
running the regressions.
 2016-01-31 23:06:59 -08:00
Palmer Dabbelt
00465b15c3 Allow the regression Makefile to clean all targets 2016-01-31 23:06:59 -08:00
Palmer Dabbelt
c9a2b7d109 Add torture as part of the regression 
Since the latest Spike fix my torture runs are succeeding, so I can now run it
as part of the regression flow.
 2016-01-31 23:06:59 -08:00
Palmer Dabbelt
e185fe6850 Add targets for emulator and fsim regressions 
This change allows the other simulation targets (the emulator and the FPGA
simulator) to be run just like the Verilog simulator could be before.
 2016-01-31 23:06:59 -08:00
Andrew Waterman
7e9d8c7256 Merge pull request #40 from ucb-bar/make-3.82 
Support make-3.82 and newer
 2016-01-28 14:28:27 -08:00
Palmer Dabbelt
1149a412cc Support make-3.82 and newer 
make changed its priorties for resolving implicit rules, which causes different
behavior when running "make run-bmark-tests".  This patch changes the hex file
rules to ensure they match between the two versions of make.

I've tried this with both make-3.81 and make-4.1, and they both work for me.
 2016-01-28 12:19:11 -08:00
Palmer Dabbelt
7209c13338 Move to a regression Makefile 
In order to have the buildbot support various types of failures it needs
to run different commands.  Rather than modifying the regression script
to have a bunch of arguments I've just gone and made a makefile for
regressions instead.

This doesn't run torture right now because that's broken, but I'll add
support soon.
 2016-01-26 22:50:49 -08:00
Howard Mao
ff79a44eb0 move some utility code from uncore to junctions 2016-01-21 15:39:09 -08:00
Andrew Waterman
fdd19145e9 bump chisel/hardfloat/junctions/uncore submodules 2016-01-17 01:50:04 -08:00
Howard Mao
04fd407c3e bump rocket submodule pointer 2016-01-15 15:29:23 -08:00
Howard Mao
3b4b7126ed Chisel3 compile-time deprecations should be runtime errors 2016-01-14 15:12:41 -08:00
Howard Mao
33aa64212d fix more Chisel3 deprecations 2016-01-14 15:06:30 -08:00
Andrew Waterman
fc638c6339 Chisel3 compatibility fixes 2016-01-12 16:28:05 -08:00
Andrew Waterman
603db5e271 Chisel3 compatibility; new NaNs; new MIPI behavior 2016-01-12 16:25:03 -08:00
Howard Mao
c06884b78c lowercase SMI to Smi 2016-01-11 17:44:10 -08:00
Colin Schmidt
8d1afa4197 bump fpga repo 2016-01-09 17:50:29 -08:00
Howard Mao
806e40d19b implement DMA streaming functionality 2016-01-07 19:26:15 -08:00
Howard Mao
2f71a3da5a bump up submodule commits to merge commits 
Github's PR system doesn't work so well with submodules, since it always
creates merge commits. We should probably avoid using it in the future.
 2015-12-22 08:09:24 -08:00
Howard Mao
0f51ca4c10 Merge pull request #35 from ucb-bar/dma 
Implement DMA unit
 2015-12-22 10:33:59 -05:00
Howard Mao
8190bf6e18 implement DMA unit 2015-12-16 21:27:48 -08:00
Howard Mao
1a272677ca more fixes to L2 cache 2015-12-16 21:06:39 -08:00
Howard Mao
560fdc19a8 add PLRU replacement option to L2 cache 2015-12-16 10:24:57 -08:00
Howard Mao
7ad9deeaee Fix issues with request merging in L2 cache and add regression tests 
In addition to the fix, there are several additions to the
RegressionTest module. The set of regressions is now parameterized and
split into ones for the cache and ones for the broadcast hub.
 2015-12-15 23:02:15 -08:00
Colin Schmidt
c080e82e92 Merge pull request #34 from seldridge/rocketchip-addons-build 
build.scala uses space-delimited ROCKETCHIP_ADDONS
 2015-12-09 11:57:19 -08:00
Schuyler Eldridge
e50e4d4c84 build.scala uses space-delimited ROCKETCHIP_ADDONS 2015-12-09 14:17:16 -05:00
Andrew Waterman
91be080526 Merge pull request #32 from ucb-bar/javamaxpermsize 
Double Java MaxPermSize.
 2015-12-07 13:58:41 -08:00
Jim Lawson
c5e9558571 Double Java MaxPermSize. 2015-12-07 12:05:06 -08:00
Howard Mao
0c91e00676 move GroundTest configs to a separate file 2015-12-06 03:01:05 -08:00
Howard Mao
4f5dabcda2 add SCR file to device tree 2015-12-05 00:28:58 -08:00
Howard Mao
6fc1e92708 add option to print cycle count regardless of exit status 2015-12-04 12:04:13 -08:00
Howard Mao
f35b83d3ca allow configuration of rocket ICache buffering 2015-12-02 17:18:39 -08:00
Howard Mao
ebf2417a32 rocc-fpu-port merged into master for rocket 2015-12-02 09:02:43 -08:00
Howard Mao
cdc476a370 change Rocc parameterization 2015-12-01 17:56:09 -08:00
Andrew Waterman
e0d849fec5 Fix zscale testing 
Use the following command in vsim:

make CONFIG=ZscaleConfig MODEL=ZscaleTop TB=ZscaleTestHarness run-asm-tests
 2015-12-01 17:31:48 -08:00
Andrew Waterman
5eeb8969f6 fix zscale build (run still fails) 2015-12-01 16:20:34 -08:00
Howard Mao
c8c68e75bb base NGenerators on NTiles, not the other way around 2015-12-01 15:26:09 -08:00