Howard Mao
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22053289ef
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fix typo rv64iu -> rv64ui
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2016-09-22 17:33:35 -07:00 |
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Henry Cook
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91aab2fabc
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no commas in yml
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2016-09-22 17:28:34 -07:00 |
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Henry Cook
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673efb400d
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Merge branch 'master' into unittest-config
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2016-09-22 16:20:53 -07:00 |
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Henry Cook
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06d8140b61
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Merge pull request #328 from ucb-bar/atomics
TileLink2 Atomics
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2016-09-22 16:20:25 -07:00 |
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Henry Cook
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1e54820f8c
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Merge remote-tracking branch 'origin/master' into unittest-config
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2016-09-22 16:03:51 -07:00 |
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Henry Cook
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411ee378de
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Provide a GeneratorApp object per user package. Extract RocketTestSuite from coreplex into rocketchip and provide GeneratorApp defaults for other target packages.
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2016-09-22 15:59:29 -07:00 |
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Henry Cook
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391be8d740
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tilelink2 RegisterRouter: minLatency is never more than 1
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2016-09-22 15:51:15 -07:00 |
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Wesley W. Terpstra
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a3e88fa13a
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tilelink2 Atomics: optimize the sign-extension circuit
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2016-09-22 15:18:54 -07:00 |
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Wesley W. Terpstra
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9f1f6fc61f
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Comparator: tolerate mismatched data when it is undefined
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2016-09-22 15:18:54 -07:00 |
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Wesley W. Terpstra
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ed038678ef
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tilelink2 Fuzzer: work around for firrtl/verilator performance issue
Big Vec()s cause very slow compilation.
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2016-09-22 15:18:54 -07:00 |
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Wesley W. Terpstra
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1e7480b6fc
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tilelink2 Monitor: work around for firrtl/verilator performance issue
Big Vec()s cause problems for these tools.
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2016-09-22 15:18:54 -07:00 |
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Wesley W. Terpstra
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ec2030df31
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tilelink2 Legacy: convert TL1 atomic operand size
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2016-09-22 15:18:54 -07:00 |
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Wesley W. Terpstra
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0a3718881f
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rocketchip: re-enable testing of atomics
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2016-09-22 15:18:54 -07:00 |
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Wesley W. Terpstra
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e5da3eb8bb
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tilelink2 Atomics: support arithmetic atomics
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2016-09-22 15:18:54 -07:00 |
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Wesley W. Terpstra
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5b80fe5b51
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tilelink2 Atomics: support Logical AMOs
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2016-09-22 15:18:54 -07:00 |
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Wesley W. Terpstra
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4066fbe18f
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tilelink2 RAMModel: exploit latency to remove bypass
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2016-09-22 15:18:54 -07:00 |
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Wesley W. Terpstra
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e0ade8c5a9
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tilelink2 Atomics: exploit minLatency to eliminate bypass
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2016-09-22 15:18:54 -07:00 |
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Wesley W. Terpstra
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3bb2580223
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tilelink2 Monitor: detect minLatency violations
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2016-09-22 15:18:54 -07:00 |
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Wesley W. Terpstra
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2b24c4b1b4
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tilelink2: most adapters can wipe away latency
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2016-09-22 15:18:54 -07:00 |
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Wesley W. Terpstra
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c115913624
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tilelink2 Buffer: increase the minLatency on ports
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2016-09-22 15:18:54 -07:00 |
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Wesley W. Terpstra
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05beb20dc4
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tilelink2: specify the minLatency for SRAM+RR
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2016-09-22 15:18:54 -07:00 |
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Wesley W. Terpstra
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44277c1db3
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tilelink2 Parameters: include a minLatency parameter for optimization
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2016-09-22 15:18:54 -07:00 |
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Wesley W. Terpstra
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cf39c32b0e
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tilelink2 Fuzzer: test Atomics
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2016-09-22 15:18:53 -07:00 |
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Wesley W. Terpstra
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2b9403633d
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tilelink2 RAMModel: support (by ignoring) atomics
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2016-09-22 15:18:53 -07:00 |
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Wesley W. Terpstra
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ce204f604a
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tilelink2 AtomicAutomata: prototype flow control complete
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2016-09-22 15:18:53 -07:00 |
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Wesley W. Terpstra
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42b10356fa
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tilelink2: add a general-purpose Arbiter
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2016-09-22 15:18:53 -07:00 |
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Wesley W. Terpstra
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7636e772c8
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tilelink2 Fuzzer: only generate legal atomics
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2016-09-22 15:18:53 -07:00 |
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Wesley W. Terpstra
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f5d604d8f8
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tilelink2 Parameters: poison ports with unsafe atomics
We need to detect if an AtomicAutomata's output ever gets mixed
with some other source of operations.
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2016-09-22 15:18:53 -07:00 |
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Wesley W. Terpstra
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d1151e2f0f
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tilelink2 Nodes: split connect into eager and lazy halves
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2016-09-22 15:18:50 -07:00 |
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Wesley W. Terpstra
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684072023f
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tilelink2 Monitor: make it a LazyModule in the hierarchy
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2016-09-22 15:14:20 -07:00 |
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Wesley W. Terpstra
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def497861b
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tilelink2 Bundles: add 1-way snoop bundles
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2016-09-22 15:14:20 -07:00 |
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Wesley W. Terpstra
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69a1f8cd1f
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tilelink2 Monitor: detect if sources are mishandled
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2016-09-22 15:14:19 -07:00 |
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Henry Cook
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83c08a931d
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[WIP] Generators for unittest and groundtest; disambiguate groundtest.TrafficGenerator
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2016-09-22 14:57:18 -07:00 |
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Wesley W. Terpstra
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3f3defb130
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Merge pull request #329 from ucb-bar/fragmenter
tilelink2 Fragmenter: Mask low bits of D channel addr_lo
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2016-09-22 14:42:55 -07:00 |
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Henry Cook
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47c5d1a992
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[WIP] Move RocketTestSuite generation into RocketchipGenerator
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2016-09-22 14:31:45 -07:00 |
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Albert Ou
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d76b762657
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tilelink2 Fragmenter: Mask low bits of D channel addr_lo
This fixes an issue where passing addr_lo through unchanged triggered
unaligned address assertions in the Monitor.
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2016-09-22 12:36:28 -07:00 |
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Howard Mao
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cd96a66ba6
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replace verilog clock divider with one written in Chisel
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2016-09-22 11:32:29 -07:00 |
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Howard Mao
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cbd702e48e
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make sure junctions and uncore unittests both run
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2016-09-21 20:17:52 -07:00 |
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mwachs5
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9acb352cf6
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Correct Merge Conflitct -- clock, not clk (#327)
I think there was a merge conflict somewhere. This should be 'clock', not 'clk'
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2016-09-21 20:02:01 -07:00 |
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Yunsup Lee
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1b1ef3be07
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simplify base Coreplex bundle
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2016-09-21 18:29:28 -07:00 |
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Yunsup Lee
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d2df6397cd
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rename trc (tile reset clock) bundles to tcr (tile clock reset)
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2016-09-21 18:29:28 -07:00 |
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Yunsup Lee
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5bb575ef74
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rename internal/external MMIO network to cbus/pbus respectively
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2016-09-21 18:29:28 -07:00 |
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mwachs5
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3a809b209f
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Allow Makefile override of RESET_DELAY (#322)
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2016-09-21 18:28:30 -07:00 |
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Henry Cook
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64fe010369
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[unittest] Config import tweaks
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2016-09-21 17:40:39 -07:00 |
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Henry Cook
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fd5e00fed9
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[coreplex] rename Testing.scala -> RocketTestSuite.scala
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2016-09-21 17:35:39 -07:00 |
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Henry Cook
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270011b768
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[unittest] more Config cleanup
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2016-09-21 17:30:14 -07:00 |
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Colin Schmidt
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2522bdd7b8
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Merge pull request #321 from ucb-bar/add-multiclock-coreplex
add multiclock support to Coreplex
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2016-09-21 17:23:34 -07:00 |
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Yunsup Lee
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7afd630d3e
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add multiclock support to Coreplex
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2016-09-21 16:55:26 -07:00 |
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Andrew Waterman
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8e63f4a1a5
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Remove ClockToSignal and vice-versa
Clock.asUInt and Bool.asClock now suffice.
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2016-09-21 16:17:14 -07:00 |
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Andrew Waterman
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2ab61f1a71
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Chisel implicit clock is now named clock, not clk
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2016-09-21 16:16:47 -07:00 |
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