Wesley W. Terpstra
5d62c321f4
generator: create annotation file
2017-10-10 23:23:06 -07:00
Henry Cook
75345b6048
rocket: don't remove ports on top module
2017-10-10 21:28:59 -07:00
Wesley W. Terpstra
5ff4c1674a
Merge pull request #1044 from freechipsproject/nicer-clint
...
clint: use RegField.toBytes to save some work
2017-10-10 20:33:00 -07:00
Wesley W. Terpstra
b3bdf5eca6
RegField: default argument for .bytes
2017-10-10 19:49:35 -07:00
Wesley W. Terpstra
e094b94ce5
clint: use RegField.toBytes to save some work
2017-10-10 19:49:35 -07:00
Wesley W. Terpstra
10472b4296
diplomacy: auto connect bundles in a stable order ( #1045 )
2017-10-10 19:41:46 -07:00
Andrew Waterman
b2bc46471b
Conditionalize some covers that are sometimes impossible ( #1043 )
2017-10-10 17:14:33 -07:00
Richard Xia
ef28ce8d2f
Merge pull request #1042 from freechipsproject/bump-riscv-tools
...
Bump riscv-tools.
2017-10-10 16:31:38 -07:00
Richard Xia
167aa7b793
Bump riscv-tools.
2017-10-10 14:14:10 -07:00
Andrew Waterman
50429daef4
Merge pull request #1036 from freechipsproject/l1-cover
...
Add some covers for L1 memory system
2017-10-10 12:28:48 -07:00
Wesley W. Terpstra
d6766a8c68
RocketTile: make sure 'hartid' is available for traits ( #1037 )
2017-10-09 21:03:18 -07:00
Andrew Waterman
a9686ab883
Merge pull request #1035 from freechipsproject/big-paddr
...
Fix paddrBits < xLen && paddrBits == vaddrBits case
2017-10-09 20:59:21 -07:00
Andrew Waterman
1474ab438d
Remove extraneous signal
2017-10-09 18:33:50 -07:00
Andrew Waterman
f3825270c1
Add some covers for L1 memory system
2017-10-09 18:33:36 -07:00
Andrew Waterman
2c4009a138
Fix paddrBits < xLen && paddrBits == vaddrBits case
...
Require and/or force vaddrBits to be bigger than paddrBits so there's
room to zero-extend a physical address by 1 bit, so that when the virtual
address is sign-extended, the sign is zero.
2017-10-09 16:48:04 -07:00
Megan Wachs
0e6aa7ae9d
Merge pull request #1024 from freechipsproject/jtag_coverage
...
Add Coverage points for JTAG TAP
2017-10-09 12:29:18 -07:00
Andrew Waterman
d78ad857ee
Merge pull request #1034 from freechipsproject/base-tile
...
Generalize Tile/Coreplex hierarchy
2017-10-09 11:42:20 -07:00
Megan Wachs
0916cf1bdd
JTAG Coverage: Correct jtag_reset case
2017-10-09 09:54:15 -07:00
Megan Wachs
9efe1c448e
Merge remote-tracking branch 'origin/master' into HEAD
2017-10-09 09:48:38 -07:00
Andrew Waterman
986cbfb6b1
For Rockets without VM, widen vaddrBits to paddrBits
...
This supports addressing a >39-bit physical address space.
2017-10-08 01:21:47 -07:00
Andrew Waterman
a0e5a20b60
Don't route branch comparison result through ALU output mux
...
This potentially mitigates a critical path, and makes the ALU usable
in processors that have dedicated branch comparators.
2017-10-07 17:36:24 -07:00
Andrew Waterman
36c39d01e4
Factor out most of HasRocketTiles into HasTiles
2017-10-07 17:36:24 -07:00
Andrew Waterman
70a4127cb8
Factor out some of HaveRocketTiles into HaveTiles
2017-10-07 17:36:24 -07:00
Andrew Waterman
34e96c03b1
Move HCF to BaseTile
2017-10-07 17:36:24 -07:00
Andrew Waterman
71205b70cc
Make RocketTileWrapper a BaseTile
2017-10-07 17:36:24 -07:00
Andrew Waterman
4645b61fd3
Decouple BaseTile from HasTileLinkMasterPort
2017-10-07 17:36:24 -07:00
Andrew Waterman
86a1953287
Merge pull request #1032 from freechipsproject/fpga_pipeline_fpu_master
...
FPU FMA FPGA retiming assist
2017-10-05 20:11:34 -07:00
Henry Styles
5498468743
FPU : simplify pipeline register generation in FMA
2017-10-05 15:18:19 -07:00
Henry Styles
7a46715cbc
FPU : to assist retiming move upto first 2 register stages of into FMA
2017-10-05 15:18:04 -07:00
Wesley W. Terpstra
bd045a3b95
tilelink: split Acquire into Acquire{Block,Perm} ( #1030 )
...
We had planned for a while to add an 'Overwrite' message which obtains
permissions without requiring retrieval of data. This is useful whenever
a master knows it will completely replace the contents of a cache block.
Instead of calling it Overwrite, we decided to split the Acquire type.
If you AcquirePerm, you MUST Release and ProbeAck with Data.
2017-10-05 12:49:49 -07:00
Wei Song (宋威)
81b9ac42a3
add comments to diplomacy resource. ( #913 )
2017-10-05 12:45:56 -07:00
Henry Cook
9040d921b5
Merge pull request #1031 from freechipsproject/non-contiguous-hartids
...
Miscellaneous multicore cleanup
2017-10-05 12:44:31 -07:00
Henry Cook
8da7aabd51
tile: supply hartid from RocketTileParams
...
make WithNCores partial configs override rather than append more tiles
2017-10-05 00:31:53 -07:00
Henry Cook
45581e60f0
Revert "Merge pull request #1027 from freechipsproject/dont-touch-hartid"
...
This reverts commit 5232a29d7d
, reversing
changes made to a2dc13669a
.
2017-10-05 00:26:44 -07:00
Andrew Waterman
5a84564203
Merge pull request #1023 from freechipsproject/csr-cleanup
...
Generalize CSR file to support simpler cores
2017-10-04 14:04:59 -07:00
Andrew Waterman
32fda51a2c
Get rid of paddrBits from SystemBus ( #1029 )
2017-10-04 12:11:37 -07:00
Andrew Waterman
7bcf28c585
Define fetchBytes in HasCoreParams, not Frontend
...
It is more generally useful.
2017-10-03 17:34:18 -07:00
Andrew Waterman
2786e42d99
Don't register interrupts in CSRFile
...
They are usually registered outside the tile in a CDC.
2017-10-03 17:34:18 -07:00
Andrew Waterman
5cfe070932
Add option to make misa read-only
2017-10-03 17:34:18 -07:00
Andrew Waterman
09468a272b
Add option to remove basic counters (mcycle/minstret)
2017-10-03 17:34:18 -07:00
Andrew Waterman
ab0821f25b
Move microarchitecture-neutral params from Rocket to Core
...
This makes some of the units more reusable.
2017-10-03 17:34:18 -07:00
Andrew Waterman
190d5c50d9
Remove deprecated custom-CSR support
2017-10-03 17:34:18 -07:00
Henry Cook
5232a29d7d
Merge pull request #1027 from freechipsproject/dont-touch-hartid
...
Make use of the new DontTouch annotation
2017-10-03 12:55:34 -07:00
Henry Cook
d33737802a
util: add DontTouch trait with dontTouchPorts method
2017-10-02 19:36:34 -07:00
Henry Cook
aa3a18222c
HellaCache: users like to peep resp.data and resp.addr
2017-10-02 19:36:30 -07:00
Henry Cook
cedfb0e784
coreplex: dontTouch the rocket_tile_inputs wire
...
which contains hartid.
2017-10-02 19:36:10 -07:00
Wesley W. Terpstra
a2dc13669a
Error grants ( #1025 )
...
* CacheCork: an error Grant still says 'toT' even though it is transient
Grants with errors must be handled by a client as though no actual
permissions were obtained, so that two clients do not both end up believing
that they own a block which is only temporarily offline. However, the
Grant MESSAGE should still match the request; ie. if you did Acquire.NtoT,
the response must be Grant.toT, even though the 'error' bit signals that
the Grant actually grants no permissions.
This keeps the implementation of request-response tracking in interstitial
adapters and FSMs simple, consistent with the way multibeat errors must
include all their beats.
* Error: handle permissions properly
2017-10-02 14:49:25 -07:00
Megan Wachs
9c9cb68462
JTAG Coverage: Add reset coverage points
2017-10-02 11:08:13 -07:00
Megan Wachs
a8ab06d572
JTAG: Add coverage points to the JTAG Tap
2017-10-02 11:08:13 -07:00
Jack Koenig
723af5e6b6
Merge pull request #971 from freechipsproject/bump-chisel-firrtl
...
Bump chisel3 and firrtl, update plugin versions
2017-09-29 17:24:12 -07:00