  Scott BeamerandYunsup Lee
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f2ca887de3
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better fpga configs
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2014-09-25 06:47:03 -07:00 |
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Scott BeamerandYunsup Lee
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1a101f8de5
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don't use latches on mem ports for fpga
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2014-09-25 06:46:21 -07:00 |
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Scott BeamerandYunsup Lee
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f4e6cd75ab
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turn off fpu for default fpga config.
a larger fpga can use defaultconfig
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2014-09-25 06:46:16 -07:00 |
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Scott Beamer
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6c6f5a3843
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add verilog target to build without simulator
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2014-09-03 17:28:45 -07:00 |
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Scott Beamer
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13b6ec4712
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including better sbt fixes
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2014-09-02 15:16:31 -07:00 |
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Scott Beamer
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26649b30ed
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fixes sbt error during first run
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2014-09-02 14:34:55 -07:00 |
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Scott Beamer
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83380053de
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use fpga backend for fpga
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2014-08-26 15:56:27 -07:00 |
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Scott Beamer
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63b62394d9
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added l2 to fpga
with new chisel & uncore, it goes into brams
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2014-08-20 15:41:07 -07:00 |
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Scott Beamer
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d3a8a224fe
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README updated for new fpga flow
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2014-08-07 14:52:56 -07:00 |
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Scott Beamer
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e390eba8ce
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convert README to markdown
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2014-08-07 14:50:31 -07:00 |
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Scott Beamer
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4109d7cc87
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newest version of chisel needed for brams
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2014-08-07 13:49:31 -07:00 |
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Scott Beamer
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cda46b3ce1
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use --recursive to populate all submodules. with current instructions you can't run tests because riscv-tests/env isn't pulled in
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2014-02-06 16:20:48 -08:00 |
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