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Author SHA1 Message Date
Andrew Waterman 728569c717 Reduce access-exception generation critical path 2017-04-18 00:47:58 -07:00
Andrew Waterman c366007a0d Tighten PMAs for LR/SC and misaligned accesses 
- LR/SC on cacheable memory only (not even scratchpad)
- No misaligned accesses on regions with get/put-effects
 2017-04-18 00:47:58 -07:00
Andrew Waterman 74a7838de0 In TLBPermissions, don't merge regions of different types 2017-04-18 00:47:58 -07:00
Andrew Waterman 7871ec82c4 Guarantee probe forward progress during LR storm 2017-04-18 00:47:58 -07:00
Andrew Waterman debcbca7de Make PMP tolerant to PA size << VA size 2017-04-17 10:28:33 -07:00
Andrew Waterman a454edaaf7 Treat exceptions as steps for the purposes of single-stepping 2017-04-17 10:28:33 -07:00
Wesley W. Terpstra 2f22fca615 rocket: reverse input edge for better output 2017-04-14 18:09:14 -07:00
Andrew Waterman fdfcffb0b2 Catch bad physical address MSBs when VA size > PA size 2017-04-14 01:03:11 -07:00
Andrew Waterman 6fbbccca3e Improve Seq indexing QoR 2017-04-14 01:03:11 -07:00
Andrew Waterman d203c4c654 Check AMO operation legality in TLB 2017-04-14 01:03:11 -07:00
Yunsup Lee 6359ff96e5 Several ScratchpadSlavePort bug fixes (#676) 
* only replicate scratch slave d-channel resp when AMO req

* dtim: port can't support put partial mask with holes

* dtim: use \!isRead instead of isAMO

* Fix ScratchpadSlavePort looking at wrong Acquire message

Rename acq to a in the helper method.
Delete isRead and isWrite altogether.
 2017-04-13 23:25:51 -07:00
Andrew Waterman b9e042d2bf Unconditionally write badaddr, possibly to zero 
59d33f6b83
 2017-04-12 13:35:02 -07:00
Andrew Waterman 470c6711a7 Do some CSE by hand, per @terpstra 2017-04-10 22:38:25 -07:00
Andrew Waterman a43bf2feae Add vectored interrupt support 
4dcaa944ba

I also added a test, which does indeed pass, but I don't want to bump
riscv-tools for that alone:

ba6d88466a
 2017-04-08 00:29:45 -07:00
Andrew Waterman c861c4925e Don't signal access exceptions on invalid PTEs 
The PPN should not be interpreted in this case.
 2017-04-05 21:46:55 -07:00
Andrew Waterman 2e09253d26 Revive I$ parity option 
Pipeline the parity check into the second stage, so that the data
RAM access + parity check do not become the critical path.
 2017-04-05 21:46:55 -07:00
Andrew Waterman 43917dd59f Get I$ s1_kill signal off the critical path 2017-04-05 21:46:55 -07:00
Andrew Waterman 744fb2e4b9 Cut imem.resp.ready critical path with a flow queue 
This is only necessary for RVC, where the decode latency is much higher.
 2017-04-05 21:46:55 -07:00
Andrew Waterman 3e72f9779f Handle single-step with a pipeline stall, not a flush 
The pipeline flush approach broke when I changed the pipeline stage
the flush happens from
 2017-04-05 19:52:44 -07:00
solomatnikov 127f121ef2 Preserve id_do_fence (#651) 2017-04-05 08:29:45 -07:00
Andrew Waterman 19f0ae64a0 Only set id_reg_fence when AMO/FENCE is actually executed 
This is a performance bug, not a correctness bug.  But randomly stalling
because of garbage bits coming out of the I$ should be avoided.

h/t @solomatnikov
 2017-04-03 21:13:52 -07:00
Andrew Waterman 410e9cf736 I$ bugfix, to be reworked 2017-03-31 12:17:41 -07:00
Henry Cook b9550e8523 Merge branch 'master' into name-rams 2017-03-30 17:36:01 -07:00
Andrew Waterman a8a2ee711c Give I$ RAMs consistent names 2017-03-30 15:50:54 -07:00
Andrew Waterman 2720095b8e Give D$ RAMs consistent names 2017-03-30 15:49:14 -07:00
Andrew Waterman 70e7e90c02 Remove splitMetadata option from L1 caches 
This is a property of the specific cache microarchitecture, not actually
an independently tunable knob.
 2017-03-30 15:48:55 -07:00
Megan Wachs 9de06f8c83 Merge remote-tracking branch 'origin/master' into debug_v013_pr 2017-03-30 08:01:11 -07:00
Andrew Waterman fd39eadcd6 New PMP encoding 2017-03-30 00:36:23 -07:00
Wesley W. Terpstra 2f2b472098 rocket: split the interrupt controller into its own node 2017-03-30 00:36:23 -07:00
Andrew Waterman 3546c8d133 If any PMPs are supported, all CSRs exist 2017-03-30 00:36:23 -07:00
Andrew Waterman 8f73a58d90 Report access exception, not page fault, if page-table walk fails 2017-03-30 00:36:23 -07:00
Andrew Waterman 25232070ec Don't redundantly set resp_ae in PTW 2017-03-30 00:36:23 -07:00
Henry Cook d3bc99e253 get local interrupts out of the tile 2017-03-30 00:36:23 -07:00
solomatnikov 0b9fc94421 Assertion for back-to-back uncached and cached ops (#631) 2017-03-29 23:07:17 -07:00
Megan Wachs d8033b20fc Merge remote-tracking branch 'origin/master' into debug_v013_pr 2017-03-29 14:58:04 -07:00
Andrew Waterman 44fb3be7d0 Fix MMIO/cache refill concurrency bug in DCache 
There's a structural hazard on s2_req, so disallow cache refill initiation
while any MMIO loads are in flight.
 2017-03-28 17:16:29 -07:00
Andrew Waterman 4215f480ef Write instruction to badaddr on illegal instruction traps 2017-03-28 00:56:14 -07:00
Megan Wachs bb64c92906 csr: Bring functionality in line with v13 spec. ebreak does not cause exception in Debug Mode, it just starts at Debug ROM again. 2017-03-27 21:21:48 -07:00
Andrew Waterman 05cbdced78 Work around zero-entry vec issue in Chisel 2017-03-27 17:57:26 -07:00
Andrew Waterman d42d8aaea7 Make SEIP writable 2017-03-27 16:37:09 -07:00
Andrew Waterman c7c357e716 Add local interrupts to core (but not yet to coreplex) 2017-03-27 16:37:09 -07:00
Andrew Waterman 069858a20c rocket: separate page faults from physical memory access exceptions 2017-03-27 16:37:09 -07:00
Andrew Waterman ea0714bfcb rocket: hard-wire UXL/SXL fields to 0 
a2a3346e73
 2017-03-27 16:37:09 -07:00
Wesley W. Terpstra 75eba294ec DCache: Release from the correct ID as well 2017-03-27 16:30:46 -07:00
Wesley W. Terpstra 4959771c97 Revert "For D$, use source 0 through N-1 for MMIO, not 1 through N" 
This reverts commit 0538dc77ce.
 2017-03-27 16:30:46 -07:00
Wesley W. Terpstra fa7ead6357 Revert "Use Reg(Vec) instead of Seq(Reg) for DCache MMIO" 
This reverts commit fb6498f2c3.
 2017-03-27 16:30:46 -07:00
Megan Wachs 08c4f7cea6 RocketTile: Create a wrapper for SyncRocketTile as well (#616) 
* RocketTile: Create a wrapper for SyncRocketTile as well

There is no guarantee that debugInterrupt is synchronous
to tlClk, even though it is true in the current implementation.
It will not be true in future implementations, as decoupling
this allows the debugInterrupt to be asserted across tlClk
gating/reset scenarios.

Therefore, even for SyncRocketTile, the debug interrupt needs to be
synchronized to coreClk, and for RationalRocketTile, 1 cycle
of synchronization is not sufficient.

Even though other interrupts may be synchronized, we just
synchronize them all to simplify the code at the expense of
a few cycles latency.

It could still be nice to use a parameter vs hard coding "3".

* RocketTile: Actually use the SyncRocketTile wrapper to get properly synchronized resets.
 2017-03-27 02:45:37 -07:00
Andrew Waterman 5d1165c850 Express PMP mask generator using a carry chain 
This allows it to be optimized like an adder, improving QoR when it
is on the critical path.
 2017-03-26 14:20:16 -07:00
Henry Cook 996a31364a rocket: remove hard-coded paddrBits (#610) 
Fall back on global variable but check that it is compatible with memory as seen from rocket's tilelink master port.
 2017-03-24 22:30:18 -07:00
Andrew Waterman 17b1ee3037 Default to 8 PMPs; support 0 PMPs 2017-03-24 16:39:52 -07:00
Andrew Waterman 97006ab396 Don't modulate PMP privilege on passsthrough when !usingVM 2017-03-24 16:39:52 -07:00
Andrew Waterman 3f0d2fe826 Instantiate PTW unconditionally 
This keeps the PMP datapaths intact.  The PTW itself will get optimized
away for the !usingVM case.
 2017-03-24 16:39:52 -07:00
Andrew Waterman 30415215b8 Don't check for exceptions on ScratchpadSlavePort accesses 2017-03-24 16:39:52 -07:00
Andrew Waterman ccd5bc9a91 Improve QoR of PMP homogeneity checker 2017-03-24 16:39:52 -07:00
Andrew Waterman e9cadf29d2 Improve DCache MMIO QoR 
No need to store the cmd field.  From the perspective of the cache, all
MMIO responses that have data can be treated the same as loads.
 2017-03-24 16:39:52 -07:00
Andrew Waterman fb6498f2c3 Use Reg(Vec) instead of Seq(Reg) for DCache MMIO 2017-03-24 16:39:52 -07:00
Andrew Waterman 0538dc77ce For D$, use source 0 through N-1 for MMIO, not 1 through N 
This makes the code a bit cleaner.
 2017-03-24 16:39:52 -07:00
Andrew Waterman 3951e57789 Force each TLB entry into its own clock-gate group 
This ameliorates a PMP critical path.

I can't figure out how to do this without asUInt/asTypeOf.
 2017-03-24 16:39:52 -07:00
Andrew Waterman 8d7f1d777e Fix an embarrassing typo in the PMPHeterogeneityChecker 2017-03-24 16:39:52 -07:00
Andrew Waterman 10c39cb8d6 Disable mprv in D-mode 2017-03-24 16:39:52 -07:00
Andrew Waterman d3bda9574c Put page homogeneity checker in PMP 
Avoids redundancy between ITLB and DTLB
 2017-03-24 16:39:52 -07:00
Andrew Waterman 9e05200e51 Don't require that PMP ranges be aligned to access size 
e.g., if a range permits access to 0x0-0xb, allow 8-byte accesses 0x0-0x7.
 2017-03-24 16:39:52 -07:00
Andrew Waterman 29e67279ba add comments 2017-03-24 16:39:52 -07:00
Andrew Waterman 4c8be13a4d Improve homogeneity circuit QoR 2017-03-24 16:39:52 -07:00
Andrew Waterman 59d6afa132 mideleg/medeleg not present without less-privileged traps 2017-03-24 16:39:52 -07:00
Andrew Waterman 38808f55d5 Share PMP mask gen between I$ and D$ 2017-03-24 16:39:52 -07:00
Andrew Waterman 86d84959cf More WIP on PMP 2017-03-24 16:39:52 -07:00
Andrew Waterman 2888779422 Flush pipeline from WB stage, not MEM 
Fixes sptbr write -> instruction translation hazard.
 2017-03-24 16:39:52 -07:00
Andrew Waterman 44ca3b60ab Retime PTW response valid bits 
It's not just to save the gate delay; it also reduces wire delay by
allowing the flops to be closer to their respective TLBs.
 2017-03-24 16:39:52 -07:00
Andrew Waterman a03556220c Default TLB size = 32 
@davidbiancolin
 2017-03-24 16:39:52 -07:00
Andrew Waterman 1875407316 Get TLB permission checks off D$ clock gating critical path 2017-03-24 16:39:52 -07:00
Andrew Waterman a4164348b4 Expose MXR to S-mode 2017-03-24 16:39:52 -07:00
Andrew Waterman 0380aed329 PUM -> SUM 2017-03-24 16:39:52 -07:00
Andrew Waterman 29414f3a23 Simplify interrupt-stack discipline 
f2ed45b179
 2017-03-24 16:39:52 -07:00
Andrew Waterman 723352c3e2 Mitigate some more PMP critical paths 2017-03-24 16:39:52 -07:00
Andrew Waterman 7484f27ed3 Don't gate exception-cause pipeline registers separately 
They are too narrow to justify gating separately from the other pipeline
registers (and one of the clock gates was on the PMP critical path).
 2017-03-24 16:39:52 -07:00
Andrew Waterman 487b8db5ef Address some PMP critical paths 2017-03-24 16:39:52 -07:00
Andrew Waterman 03fb334c4c Take mprv calculation off critical path 2017-03-24 16:39:52 -07:00
Andrew Waterman f0796f0509 Pass correct access size information to PMP checker 2017-03-24 16:39:52 -07:00
Andrew Waterman a6874c03f7 Remove DecoupledTLB 2017-03-24 16:39:52 -07:00
Andrew Waterman 78f9f6b9ef When SFENCE.VMA has rs2 != x0, don't flush global mappings 2017-03-24 16:39:52 -07:00
Andrew Waterman 1b950128e1 PTW should always use S-mode privilege 
If an exception occurs while a page-table walk is coincidentally in
progress (e.g., an illegal instruction executes during data TLB refill),
then the processor might enter M-mode.  However, the PTW's accesses
should proceed without M privilege, to avoid bypassing PMPs.

Note, the same argument doesn't apply to the nonblocking cache's replay
queues, because those accesses have already been checked against the PMPs.
The cache correctly ignores access exceptions reported on replays,
provided no exceptions were reported on the initial access.
 2017-03-24 16:39:52 -07:00
Andrew Waterman aace526857 WIP on PMP 2017-03-24 16:39:52 -07:00
Andrew Waterman b1b405404d Set PRV=M when entering debug mode 
Debug mode mostly behaves like M-mode, so this approach avoids having
to check the debug bit in most permission checks.
 2017-03-24 16:39:52 -07:00
Andrew Waterman cf168e419b Support SFENCE.VMA rs1 argument 
This one's a little invasive.  To flush a specific entry from the TLB, you
need to reuse its CAM port.  Since the TLB lookup can be on the critical
path, we wish to avoid muxing in another address.

This is simple on the data side, where the datapath already carries rs1 to
the TLB (it's the same path as the AMO address calculation).  It's trickier
for the I$, where the TLB lookup address comes from the fetch stage PC.
The trick is to temporarily redirect the PC to rs1, then redirect the PC
again to the instruction after SFENCE.VMA.
 2017-03-24 16:39:52 -07:00
Henry Cook 055b8ba1f0 rocket: avoid LinkedHashMap.keys to preserve traversal order (#603) 2017-03-22 14:38:33 -07:00
Andrew Waterman 3609254e4a There's no structural hazard on MMIO store responses 
So don't stall as though there were.
 2017-03-21 14:17:32 -07:00
Yunsup Lee 5eae7e1da4 make DCache s1_nack less conservative for pipelined MMIO requests 2017-03-21 11:16:51 -07:00
Wesley W. Terpstra 4c00066746 rocket: describe dcache as two clients (fifo+cached) 2017-03-21 11:16:51 -07:00
Wesley W. Terpstra 278f6fea24 tilelink2: define is{Request,Response} based on spec 2017-03-20 13:41:02 -07:00
Wesley W. Terpstra 0c92283a61 rocket icache: tie off b ready 2017-03-19 17:18:50 -07:00
Andrew Waterman d6f571cbbb Implement mstatus.TSR 2017-03-13 14:50:06 -07:00
Andrew Waterman 1fea0460ba Support superpage entries in TLB 2017-03-13 14:50:06 -07:00
Andrew Waterman 2d267b4940 Support corner cases in TLBPermissions 
Don't crap out if the yes-set or no-set is empty.
 2017-03-13 14:50:06 -07:00
Wesley W. Terpstra c847559853 TLB: add a helper API to determine homogeneous page permissions 2017-03-13 14:50:06 -07:00
Henry Cook dbc8f4b30b last => done 2017-03-10 15:58:38 -08:00
Andrew Waterman 380c10f7bd Zap conflicting TLB entries, preparing for superpage support 
Superpages create the possibility that two entries in the TLB may match.
This corresponds to a software bug, but we can't return complete garbage;
we must return either the old translation or the new translation.  This
isn't compatible with the Mux1H approach.  So, flush the TLB and report
a miss on duplicate entries.
 2017-03-10 15:58:23 -08:00
Andrew Waterman b24c43badb Don't double-count release traffic in perfctrs 2017-03-09 16:49:02 -08:00
Andrew Waterman 4f8f05d635 Add performance counter facility 2017-03-09 13:58:50 -08:00
Andrew Waterman 24a2278fc4 Perform all illegal-instruction detection in ID stage 
This is simpler, reduces what would have become a critical path in
the commit stage, and will make it easier to support the mbadinst
CSR if it is implemented.
 2017-03-09 11:29:51 -08:00
Andrew Waterman 7668827741 Support unrolling the integer divider 2017-03-09 11:29:51 -08:00
Andrew Waterman 74d8d672bf Improve BTB critical path at slight accuracy cost 
Make entries fully associative on lower 14 bits only, not full address.
 2017-03-09 11:29:51 -08:00
Andrew Waterman 11c8857b5d Don't re-read I$ RAMs on stall 2017-03-09 11:29:51 -08:00
Andrew Waterman db0a02b78e WIP on priv-1.10 2017-03-09 11:29:51 -08:00
Wesley W. Terpstra 43dea38ee9 dcache: we need the bits within the beat so select the right word (#575) 
We now have confirmation that it fixed the problem.
 2017-03-08 00:19:09 -08:00
Henry Cook d0ae087587 rocket: allow scratchpad address to be configurable (#570) 2017-03-06 21:35:45 -08:00
Wesley W. Terpstra 676974281a rocket: describe dcache scratchpad as memory 2017-03-03 02:54:48 -08:00
Wesley W. Terpstra 8e4f348dda rocket: if no MMU, don't print it in DTS 2017-03-03 00:48:26 -08:00
Wesley W. Terpstra 4535de2669 rocket: use diplomatic interrupts 
This makes it possible for the PLIC to work with heterogenous cores.
 2017-03-02 21:19:23 -08:00
Wesley W. Terpstra 5bd9f18e5b rocket: add dts cpu description 2017-03-02 21:19:22 -08:00
Wesley W. Terpstra fd972f5c67 icache: back-pressure is unnecessary (#564) 
* icache: back-pressure is unnecessary
* icache: require that the response arrives after the request
 2017-02-24 21:01:56 -08:00
Wesley W. Terpstra 3931b0faff coreplex: assume L1 runs no slower than L2 2017-02-17 15:15:41 +01:00
Henry Cook e8c8d2af71 Heterogeneous Tiles (#550) 
Fundamental new features:

* Added tile package: This package is intended to hold components re-usable across different types of tile. Will be the future location of TL2-RoCC accelerators and new diplomatic versions of intra-tile interfaces.
* Adopted [ModuleName]Params convention: Code base was very inconsistent about what to name case classes that provide parameters to modules. Settled on calling them [ModuleName]Params to distinguish them from config.Parameters and config.Config. So far applied mostly only to case classes defined within rocket and tile.
* Defined RocketTileParams: A nested case class containing case classes for all the components of a tile (L1 caches and core). Allows all such parameters to vary per-tile.
* Defined RocketCoreParams: All the parameters that can be varied per-core.
* Defined L1CacheParams: A trait defining the parameters common to L1 caches, made concrete in different derived case classes.
* Defined RocketTilesKey: A sequence of RocketTileParams, one for every tile to be created.
* Provided HeterogeneousDualCoreConfig: An example of making a heterogeneous chip with two cores, one big and one little.
* Changes to legacy code: ReplacementPolicy moved to package util. L1Metadata moved to package tile. Legacy L2 cache agent removed because it can no longer share the metadata array implementation with the L1. Legacy GroundTests on life support.

Additional changes that got rolled in along the way:

* rocket: 	Fix critical path through BTB for I$ index bits > pgIdxBits
* coreplex: tiles connected via :=*
* groundtest: updated to use TileParams
* tilelink: cache cork requirements are relaxed to allow more cacheless masters
 2017-02-09 13:59:09 -08:00
Andrew Waterman 8225676a86 For FMIN(sNaN, x) and FMIN(qNaN, qNaN), return canonical NaN 
See https://github.com/riscv/riscv-isa-sim/issues/76
 2017-02-02 11:55:08 -08:00
Andrew Waterman 75edf42323 Set xPIE=1 on xRET 
We were setting xPIE=0 instead.  This is a benign bug, but still a bug.
 2017-02-02 11:55:08 -08:00
Wesley W. Terpstra 9ca8f514c0 rocket: creating Bundles in an object also break dedup! 2017-01-31 14:45:11 -08:00
Wesley W. Terpstra e5af59db68 rocketchip: work-around ucb-bar/chisel3#472 2017-01-31 14:20:02 -08:00
Wesley W. Terpstra 972953868c uncore: switch to new diplomacy Node API 
Most adapters should work on multiple ports.
This patch changes them all.
 2017-01-29 15:54:45 -08:00
Wesley W. Terpstra 03f2fe02ac coreplex: support rational crossing to L2 (#534) 2017-01-27 17:09:43 -08:00
Wesley W. Terpstra 5d70265e86 rocket: L1 only needs cache-line transfer sizes 2017-01-19 19:07:14 -08:00
Wesley W. Terpstra bf7823f1c8 tilelink2: split suportsAcquire into T and B variants 2017-01-19 19:07:13 -08:00
Henry Cook c1b7c84f09 [rocket] bugfix: RoccExampleConfig looks up PAddrBits too early 2017-01-19 17:48:04 -08:00
Henry Cook 307f938b88 [rocket] bugfix: fixes #517 2017-01-19 17:48:04 -08:00
Henry Cook 74b6a8d02b Refactor Tile to use cake pattern (#502) 
* [rocket] Refactor Tile into cake pattern with traits
* [rocket] cacheDataBits &etc in HasCoreParameters
* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters
* [rocket] frontend and icache now diplomatic
* [rocket] file name capitalization
* [rocket] re-add hook for inserting externally-defined Cores
* [rocket] add FPUCoreIO
* [groundtest] move TL1 Config instances to where they are used
* [unittest] remove legacy unit tests
* [groundtest] remove legacy device tests
 2017-01-16 18:24:08 -08:00
Andrew Waterman 71c4b000b3 Don't special-case power-of-2 replacement policy for BTB 
PLRU wasn't implemented correctly for the BTB, since it wasn't
increasing the priority on replacement, only on usage.  Regardless,
this should be a second-order effect, so using FIFO always is fine.
 2017-01-11 13:21:55 -08:00
Henry Cook 540502f96d Convert frontend and icache to diplomacy/tl2 (#486) 
* [rocket] file capitalization

* [rocket] cacheDataBits &etc in HasCoreParameters

* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters

* [rocket] frontend and icache now diplomatic
 2016-12-12 17:38:55 -08:00
Wesley W. Terpstra 020fbe8be9 diplomacy: make config.Parameters available in bundle connect() 
This makes it posisble to use Parameters to control Monitors.
However, we need to make all LazyModules carry Parameters.
 2016-12-07 12:24:01 -08:00
Andrew Waterman 915697cb09 Fix FEQ flag generation (#479) 
FEQ is not a signaling comparison (i.e., qNaN is not an invalid input).

Also, minor code cleanup.
 2016-12-06 11:54:29 -08:00
Schuyler Eldridge 36fe024671 CacheName no longer needed in RoCCInterface 
With dcacheParams passed to a RoCC, the CacheName no longer needs to be
specified.
 2016-12-04 19:01:39 -08:00
Schuyler Eldridge 624db2034b Make instantiated RoCC use dcacheParams 2016-12-04 19:01:39 -08:00
Wesley W. Terpstra b7963eca4e copyright: ran scripts/modify-copyright 2016-11-27 22:15:43 -08:00
Wesley W. Terpstra 4146f6a792 TLB: do not access illegal addresses (#460) 2016-11-26 15:11:42 -08:00
Wesley W. Terpstra 1e0aca7358 dcache: the high bit of s2_req.typ is the SIGN bit (not size) (#455) 2016-11-25 15:26:22 -08:00
Henry Cook 38c5af5bad [rocket] cleanup mshr logic 2016-11-23 12:09:56 -08:00
Henry Cook dae6772624 factor out common cache subcomponents into uncore.util 2016-11-23 12:09:35 -08:00
Henry Cook c65c255815 [coreplex] TileId moved to groundtest 2016-11-23 12:08:45 -08:00
Andrew Waterman 5f3fb64ef0 Per ABI, only x1 and x5 should be treated as function returns 
We were doing so for x3 and x7, as well, which could reduce performance
for compilers that happen to perform indirect jumps via t2 (x7).
 2016-11-22 12:01:05 -08:00
Wesley W. Terpstra 5fe107bb07 rocket: pass scratchpad address to block dcache 2016-11-21 21:13:26 -08:00
Wesley W. Terpstra c18bc07bbc TLB: determine RWX from TL2 properties directly 2016-11-21 21:13:26 -08:00
Henry Cook 28c6be90ab [rocket] require refillcycesperbeat == 1 and remove flowthroughserializer 2016-11-20 19:36:51 -08:00
Henry Cook ff9b5bf8fc [rocket] nbdcache release bugfix 2016-11-20 19:07:06 -08:00
Henry Cook 3f47d5b5eb [rocket] re-enable working NBDcache (passes Tracegen) 2016-11-19 19:19:16 -08:00
Colin Schmidt 9dd12545d0 [Rocket] Send correct type for iomshr reqs 
Also contain grow param bugfix
 2016-11-19 19:04:06 -08:00
Wesley W. Terpstra 32a1c27441 rocket: disable nbdcache until it's fully ported 2016-11-18 19:55:24 -08:00
Wesley W. Terpstra 452bb2fc80 dcache fix TinyConfig 2016-11-18 19:50:34 -08:00
Henry Cook 2976fd84e4 [rocket] resolve cde/config conflicts 2016-11-18 19:11:34 -08:00
Henry Cook 8b908465e0 [tl2] convert NBDcache to TL2 (WIP; compiles but untested) 2016-11-18 19:04:06 -08:00
Wesley W. Terpstra 37a3c22639 rocketchip: move from using cde to config 2016-11-18 16:18:33 -08:00
Wesley W. Terpstra 30425d1665 rocketchip: eliminate all Knobs 2016-11-18 14:31:42 -08:00
Henry Cook 5bd343bac8 [rocket] d_last && d.fire() => d_done 2016-11-17 18:42:59 -08:00