Henry Cook
91aab2fabc
no commas in yml
2016-09-22 17:28:34 -07:00
Henry Cook
673efb400d
Merge branch 'master' into unittest-config
2016-09-22 16:20:53 -07:00
Henry Cook
06d8140b61
Merge pull request #328 from ucb-bar/atomics
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TileLink2 Atomics
2016-09-22 16:20:25 -07:00
Henry Cook
1e54820f8c
Merge remote-tracking branch 'origin/master' into unittest-config
2016-09-22 16:03:51 -07:00
Henry Cook
411ee378de
Provide a GeneratorApp object per user package. Extract RocketTestSuite from coreplex into rocketchip and provide GeneratorApp defaults for other target packages.
2016-09-22 15:59:29 -07:00
Henry Cook
391be8d740
tilelink2 RegisterRouter: minLatency is never more than 1
2016-09-22 15:51:15 -07:00
Wesley W. Terpstra
a3e88fa13a
tilelink2 Atomics: optimize the sign-extension circuit
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
9f1f6fc61f
Comparator: tolerate mismatched data when it is undefined
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
ed038678ef
tilelink2 Fuzzer: work around for firrtl/verilator performance issue
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Big Vec()s cause very slow compilation.
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
1e7480b6fc
tilelink2 Monitor: work around for firrtl/verilator performance issue
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Big Vec()s cause problems for these tools.
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
ec2030df31
tilelink2 Legacy: convert TL1 atomic operand size
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
0a3718881f
rocketchip: re-enable testing of atomics
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
e5da3eb8bb
tilelink2 Atomics: support arithmetic atomics
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
5b80fe5b51
tilelink2 Atomics: support Logical AMOs
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
4066fbe18f
tilelink2 RAMModel: exploit latency to remove bypass
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
e0ade8c5a9
tilelink2 Atomics: exploit minLatency to eliminate bypass
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
3bb2580223
tilelink2 Monitor: detect minLatency violations
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
2b24c4b1b4
tilelink2: most adapters can wipe away latency
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
c115913624
tilelink2 Buffer: increase the minLatency on ports
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
05beb20dc4
tilelink2: specify the minLatency for SRAM+RR
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
44277c1db3
tilelink2 Parameters: include a minLatency parameter for optimization
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
cf39c32b0e
tilelink2 Fuzzer: test Atomics
2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
2b9403633d
tilelink2 RAMModel: support (by ignoring) atomics
2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
ce204f604a
tilelink2 AtomicAutomata: prototype flow control complete
2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
42b10356fa
tilelink2: add a general-purpose Arbiter
2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
7636e772c8
tilelink2 Fuzzer: only generate legal atomics
2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
f5d604d8f8
tilelink2 Parameters: poison ports with unsafe atomics
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We need to detect if an AtomicAutomata's output ever gets mixed
with some other source of operations.
2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
d1151e2f0f
tilelink2 Nodes: split connect into eager and lazy halves
2016-09-22 15:18:50 -07:00
Wesley W. Terpstra
684072023f
tilelink2 Monitor: make it a LazyModule in the hierarchy
2016-09-22 15:14:20 -07:00
Wesley W. Terpstra
def497861b
tilelink2 Bundles: add 1-way snoop bundles
2016-09-22 15:14:20 -07:00
Wesley W. Terpstra
69a1f8cd1f
tilelink2 Monitor: detect if sources are mishandled
2016-09-22 15:14:19 -07:00
Henry Cook
83c08a931d
[WIP] Generators for unittest and groundtest; disambiguate groundtest.TrafficGenerator
2016-09-22 14:57:18 -07:00
Wesley W. Terpstra
3f3defb130
Merge pull request #329 from ucb-bar/fragmenter
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tilelink2 Fragmenter: Mask low bits of D channel addr_lo
2016-09-22 14:42:55 -07:00
Henry Cook
47c5d1a992
[WIP] Move RocketTestSuite generation into RocketchipGenerator
2016-09-22 14:31:45 -07:00
Albert Ou
d76b762657
tilelink2 Fragmenter: Mask low bits of D channel addr_lo
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This fixes an issue where passing addr_lo through unchanged triggered
unaligned address assertions in the Monitor.
2016-09-22 12:36:28 -07:00
Howard Mao
cd96a66ba6
replace verilog clock divider with one written in Chisel
2016-09-22 11:32:29 -07:00
Howard Mao
cbd702e48e
make sure junctions and uncore unittests both run
2016-09-21 20:17:52 -07:00
mwachs5
9acb352cf6
Correct Merge Conflitct -- clock, not clk ( #327 )
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I think there was a merge conflict somewhere. This should be 'clock', not 'clk'
2016-09-21 20:02:01 -07:00
Yunsup Lee
1b1ef3be07
simplify base Coreplex bundle
2016-09-21 18:29:28 -07:00
Yunsup Lee
d2df6397cd
rename trc (tile reset clock) bundles to tcr (tile clock reset)
2016-09-21 18:29:28 -07:00
Yunsup Lee
5bb575ef74
rename internal/external MMIO network to cbus/pbus respectively
2016-09-21 18:29:28 -07:00
mwachs5
3a809b209f
Allow Makefile override of RESET_DELAY ( #322 )
2016-09-21 18:28:30 -07:00
Henry Cook
64fe010369
[unittest] Config import tweaks
2016-09-21 17:40:39 -07:00
Henry Cook
fd5e00fed9
[coreplex] rename Testing.scala -> RocketTestSuite.scala
2016-09-21 17:35:39 -07:00
Henry Cook
270011b768
[unittest] more Config cleanup
2016-09-21 17:30:14 -07:00
Colin Schmidt
2522bdd7b8
Merge pull request #321 from ucb-bar/add-multiclock-coreplex
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add multiclock support to Coreplex
2016-09-21 17:23:34 -07:00
Yunsup Lee
7afd630d3e
add multiclock support to Coreplex
2016-09-21 16:55:26 -07:00
Andrew Waterman
8e63f4a1a5
Remove ClockToSignal and vice-versa
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Clock.asUInt and Bool.asClock now suffice.
2016-09-21 16:17:14 -07:00
Andrew Waterman
2ab61f1a71
Chisel implicit clock is now named clock, not clk
2016-09-21 16:16:47 -07:00
Henry Cook
335e866176
[unittest] Parallelize UnitTestSuite ( #319 )
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* [unittest] Parallelize UnitTestSuite so all tests have their own timer, runs until all finish or any timeout. Adds SimpleTimer.
* [util] Timer spacing cleanup
* [unittest] Remove Config reference to UnitTestTimeout
2016-09-21 13:05:22 -07:00
