Add support for FSDB waveform dumping using existing API. Feature is enabled using +define+FSDB.
Change has not been fully regressed (i.e., please don't pull blindly). Impact on existing knobs is minimal, should not affect existing functionality. Automated Travis builds should be sufficient to assess.
Alternatively could using +define+VCS. Chose to introduce new define because multiple simulators support FSDB dumping.
If user compiles without +define+DEBUG but then requests +vcdfile at
simulation time, that request would be silently ignored. This changes
it to a fatal error.
It's good philosophy to treat plusargs like +vcdfile as commands, not
suggestions, and die immediately if they cannot be honored, instead of
silently ignoring them. Otherwise the user sits through the entire
simulation and then is left scratching his head wondering where his
waveforms are.
This fixes the following compile warnings and simulation errors:
Compile-time warnings:
$vcdplusfile(vcdplusfile);
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ncelab: *W,MISSYST (/home/scottj/rocket-chip/vsrc/TestDriver.v,42|17): Unrecognized system task or function: $vcdplusfile (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].
$vcdpluson(0);
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ncelab: *W,MISSYST (/home/scottj/rocket-chip/vsrc/TestDriver.v,43|15): Unrecognized system task or function: $vcdpluson (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].
$vcdplusmemon(0);
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ncelab: *W,MISSYST (/home/scottj/rocket-chip/vsrc/TestDriver.v,44|18): Unrecognized system task or function: $vcdplusmemon (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].
`VCDPLUSCLOSE
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ncelab: *W,MISSYST (/home/scottj/rocket-chip/vsrc/TestDriver.v,89|20): Unrecognized system task or function: $vcdplusclose (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].
Which then become simulation-time errors:
$vcdplusfile(vcdplusfile);
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ncsim: *E,MSSYSTF (/home/scottj/rocket-chip/vsrc/TestDriver.v,42|17): User Defined system task or function ($vcdplusfile) registered during elaboration and used within the simulation has not been registered during simulation.
$vcdpluson(0);
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ncsim: *E,MSSYSTF (/home/scottj/rocket-chip/vsrc/TestDriver.v,43|15): User Defined system task or function ($vcdpluson) registered during elaboration and used within the simulation has not been registered during simulation.
$vcdplusmemon(0);
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ncsim: *E,MSSYSTF (/home/scottj/rocket-chip/vsrc/TestDriver.v,44|18): User Defined system task or function ($vcdplusmemon) registered during elaboration and used within the simulation has not been registered during simulation.
`VCDPLUSCLOSE
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ncsim: *E,MSSYSTF (/home/scottj/rocket-chip/vsrc/TestDriver.v,89|20): User Defined system task or function ($vcdplusclose) registered during elaboration and used within the simulation has not been registered during simulation.
`VCDPLUSCLOSE
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ncsim: *E,MSSYSTF (/home/scottj/rocket-chip/vsrc/TestDriver.v,97|20): User Defined system task or function ($vcdplusclose) registered during elaboration and used within the simulation has not been registered during simulation.
The SystemVerilog LRM (IEEE 1800-2012) clause 20.15.1 ($random
function) says: "The seed argument shall be an integral variable."
This fixes the following compile warning:
rand_value = $random($urandom);
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ncelab: *W,WRNOTL (/home/scottj/rocket-chip/vsrc/TestDriver.v,34|23): Argument to out parameter is not a legal lvalue.
This is an unavoidably invasive commit, because it affects the unit tests
(which formerly exited using stop()), the test harness Verilog generator
(since it is no longer necessary), and the DRAM model (since it is no
longer connected). However, this should substantially reduce the effort
of building test harnesses in the future, since manual or semi-automatic
Verilog writing should no longer be necessary. Furthermore, there is now
very little duplication of effort between the Verilator and VCS test
harnesses.
This commit removes support for DRAMsim, which is a bit of an unfortunate
consequence. The main blocker is the lack of Verilog parameterization for
BlackBox. It would be straightforward to revive DRAMsim once support for
that feature is added to Chisel and FIRRTL. But that might not even be
necessary, as we move towards synthesizable DRAM models and FAME-1
transformations.
