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Commit Graph

20 Commits

Author SHA1 Message Date
Edmond Cote
42e5e92d43
Update TestDriver module to support FSDB
Add support for FSDB waveform dumping using existing API.  Feature is enabled using +define+FSDB.

Change has not been fully regressed (i.e., please don't pull blindly).  Impact on existing knobs is minimal, should not affect existing functionality.  Automated Travis builds should be sufficient to assess.

Alternatively could using +define+VCS.  Chose to introduce new define because multiple simulators support FSDB dumping.
2018-01-09 09:54:34 -08:00
Andrew Waterman
2faf8ea239 Add +dump-start=N option to VCS
Starts dumping waveform on cycle N.

Can control stop cycle with +max-cycles.
2017-04-20 17:00:46 -07:00
Wesley W. Terpstra
b7963eca4e copyright: ran scripts/modify-copyright 2016-11-27 22:15:43 -08:00
Scott Johnson
f382ee70da Sanity check compile-time vs simulation-time options
If user compiles without +define+DEBUG but then requests +vcdfile at
simulation time, that request would be silently ignored. This changes
it to a fatal error.

It's good philosophy to treat plusargs like +vcdfile as commands, not
suggestions, and die immediately if they cannot be honored, instead of
silently ignoring them. Otherwise the user sits through the entire
simulation and then is left scratching his head wondering where his
waveforms are.
2016-10-24 14:45:34 -07:00
Colin Schmidt
737cf82478 Print out seed if we can (#412)
Now that we have ifdef VCS in here lets use it for something more than compatibility
2016-10-24 12:36:29 -07:00
Scott Johnson
a919a280e8 Fix Cadence Incisive compile errors; VCD-Plus is a VCS-only format
This fixes the following compile warnings and simulation errors:

Compile-time warnings:
      $vcdplusfile(vcdplusfile);
                 |
ncelab: *W,MISSYST (/home/scottj/rocket-chip/vsrc/TestDriver.v,42|17): Unrecognized system task or function: $vcdplusfile (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].
      $vcdpluson(0);
               |
ncelab: *W,MISSYST (/home/scottj/rocket-chip/vsrc/TestDriver.v,43|15): Unrecognized system task or function: $vcdpluson (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].
      $vcdplusmemon(0);
                  |
ncelab: *W,MISSYST (/home/scottj/rocket-chip/vsrc/TestDriver.v,44|18): Unrecognized system task or function: $vcdplusmemon (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].
        `VCDPLUSCLOSE
                    |
ncelab: *W,MISSYST (/home/scottj/rocket-chip/vsrc/TestDriver.v,89|20): Unrecognized system task or function: $vcdplusclose (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].

Which then become simulation-time errors:

      $vcdplusfile(vcdplusfile);
                 |
ncsim: *E,MSSYSTF (/home/scottj/rocket-chip/vsrc/TestDriver.v,42|17): User Defined system task or function ($vcdplusfile) registered during elaboration and used within the simulation has not been registered during simulation.
      $vcdpluson(0);
               |
ncsim: *E,MSSYSTF (/home/scottj/rocket-chip/vsrc/TestDriver.v,43|15): User Defined system task or function ($vcdpluson) registered during elaboration and used within the simulation has not been registered during simulation.
      $vcdplusmemon(0);
                  |
ncsim: *E,MSSYSTF (/home/scottj/rocket-chip/vsrc/TestDriver.v,44|18): User Defined system task or function ($vcdplusmemon) registered during elaboration and used within the simulation has not been registered during simulation.
        `VCDPLUSCLOSE
                    |
ncsim: *E,MSSYSTF (/home/scottj/rocket-chip/vsrc/TestDriver.v,89|20): User Defined system task or function ($vcdplusclose) registered during elaboration and used within the simulation has not been registered during simulation.
        `VCDPLUSCLOSE
                    |
ncsim: *E,MSSYSTF (/home/scottj/rocket-chip/vsrc/TestDriver.v,97|20): User Defined system task or function ($vcdplusclose) registered during elaboration and used within the simulation has not been registered during simulation.
2016-10-19 13:26:31 -07:00
Scott Johnson
9f0fda01b3 Fix Cadence Incisive compile warning
The SystemVerilog LRM (IEEE 1800-2012) clause 20.15.1 ($random
function) says: "The seed argument shall be an integral variable."

This fixes the following compile warning:

    rand_value = $random($urandom);
                       |
ncelab: *W,WRNOTL (/home/scottj/rocket-chip/vsrc/TestDriver.v,34|23): Argument to out parameter is not a legal lvalue.
2016-10-19 13:23:36 -07:00
Scott Johnson
dc4c375c7f Silence Verilog compile warning from Cadence Incisive 2016-10-17 15:44:24 -07:00
Yunsup Lee
23c8b06d4a use $urandom as seed for $random 2016-10-03 17:56:30 -07:00
Yunsup Lee
5ff3d3d61c correctly initialize with seed 2016-10-02 17:31:32 -07:00
mwachs5
9acb352cf6 Correct Merge Conflitct -- clock, not clk (#327)
I think there was a merge conflict somewhere. This should be 'clock', not 'clk'
2016-09-21 20:02:01 -07:00
mwachs5
3a809b209f Allow Makefile override of RESET_DELAY (#322) 2016-09-21 18:28:30 -07:00
Andrew Waterman
2ab61f1a71 Chisel implicit clock is now named clock, not clk 2016-09-21 16:16:47 -07:00
Henry Cook
9e2b0aad65 Revert "allow MODEL to be something other than TestHarness"
This reverts commit bf253aaa97.
2016-09-15 11:53:05 -07:00
Howard Mao
bf253aaa97 allow MODEL to be something other than TestHarness 2016-09-14 20:51:56 -07:00
Scott Johnson
96a868d388 enable the TestDriver to be used in a SystemVerilog UVM-based testbench, which has its own way to manage end-of-simulation and does not like anyone else to call $finish 2016-08-19 17:14:54 -07:00
Scott Johnson
2d12f6689c make CLOCK_PERIOD actually be the clock period, instead of half of the clock period 2016-08-19 16:55:57 -07:00
Scott Johnson
4dbcc568dc reorder code to get rid of messy -1 2016-08-19 16:55:57 -07:00
Scott Johnson
f945acf712 rm race condition on trace_count 2016-08-19 16:55:57 -07:00
Andrew Waterman
ed827678ac Write test harness in Chisel
This is an unavoidably invasive commit, because it affects the unit tests
(which formerly exited using stop()), the test harness Verilog generator
(since it is no longer necessary), and the DRAM model (since it is no
longer connected).  However, this should substantially reduce the effort
of building test harnesses in the future, since manual or semi-automatic
Verilog writing should no longer be necessary.  Furthermore, there is now
very little duplication of effort between the Verilator and VCS test
harnesses.

This commit removes support for DRAMsim, which is a bit of an unfortunate
consequence.  The main blocker is the lack of Verilog parameterization for
BlackBox.  It would be straightforward to revive DRAMsim once support for
that feature is added to Chisel and FIRRTL.  But that might not even be
necessary, as we move towards synthesizable DRAM models and FAME-1
transformations.
2016-08-15 23:27:27 -07:00