91 lines
1.8 KiB
Verilog
91 lines
1.8 KiB
Verilog
// See LICENSE for license details.
|
|
|
|
module TestDriver;
|
|
|
|
reg clk = 1'b0;
|
|
reg reset = 1'b1;
|
|
|
|
always #`CLOCK_PERIOD clk = ~clk;
|
|
initial #777.7 reset = 0;
|
|
|
|
// Read input arguments and initialize
|
|
reg verbose = 1'b0;
|
|
wire printf_cond = verbose && !reset;
|
|
reg [63:0] max_cycles = 0;
|
|
reg [63:0] trace_count = 0;
|
|
reg [1023:0] vcdplusfile = 0;
|
|
reg [1023:0] vcdfile = 0;
|
|
initial
|
|
begin
|
|
$value$plusargs("max-cycles=%d", max_cycles);
|
|
verbose = $test$plusargs("verbose");
|
|
`ifdef DEBUG
|
|
if ($value$plusargs("vcdplusfile=%s", vcdplusfile))
|
|
begin
|
|
$vcdplusfile(vcdplusfile);
|
|
$vcdpluson(0);
|
|
$vcdplusmemon(0);
|
|
end
|
|
|
|
if ($value$plusargs("vcdfile=%s", vcdfile))
|
|
begin
|
|
$dumpfile(vcdfile);
|
|
$dumpvars(0, testHarness);
|
|
$dumpon;
|
|
end
|
|
`define VCDPLUSCLOSE $vcdplusclose; $dumpoff;
|
|
`else
|
|
`define VCDPLUSCLOSE
|
|
`endif
|
|
end
|
|
|
|
reg [255:0] reason = "";
|
|
reg failure = 1'b0;
|
|
wire success;
|
|
integer stderr = 32'h80000002;
|
|
always @(posedge clk)
|
|
begin
|
|
if (!reset)
|
|
begin
|
|
if (max_cycles > 0 && trace_count > max_cycles)
|
|
begin
|
|
reason = " (timeout)";
|
|
failure = 1'b1;
|
|
end
|
|
|
|
if (failure)
|
|
begin
|
|
$fdisplay(stderr, "*** FAILED ***%s after %d simulation cycles", reason, trace_count);
|
|
`VCDPLUSCLOSE
|
|
$fatal;
|
|
end
|
|
|
|
if (success)
|
|
begin
|
|
if (verbose)
|
|
$fdisplay(stderr, "Completed after %d simulation cycles", trace_count);
|
|
`VCDPLUSCLOSE
|
|
$finish;
|
|
end
|
|
end
|
|
end
|
|
|
|
always @(posedge clk)
|
|
begin
|
|
trace_count = trace_count + 1;
|
|
`ifdef GATE_LEVEL
|
|
if (verbose)
|
|
begin
|
|
$fdisplay(stderr, "C: %10d", trace_count-1);
|
|
end
|
|
`endif
|
|
end
|
|
|
|
TestHarness testHarness(
|
|
.clk(clk),
|
|
.reset(reset),
|
|
.io_success(success)
|
|
);
|
|
|
|
endmodule
|