riscv/rocket-chip
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Author SHA1 Message Date
Andrew Waterman
d93d7b9fa4 Only merge stores that aren't yet pending 
This fixes a deadlock (and possibly memory corruption, though that is
unconfirmed).  The following sequence manifests it, assuming t0
is 32-byte aligned:

    sw t0, 0(t0)
    sw t0, 16(t0)
    lw t1, 4(t0)
    lw t2, 4(t0)
 2017-09-17 15:01:07 -07:00
Megan Wachs
c85333f826 Merge remote-tracking branch 'origin/test_mode_reset' into test_mode_reset 2017-09-17 13:51:46 -07:00
Megan Wachs
215e072e5c test_mode_reset: fix typos 2017-09-17 13:51:40 -07:00
Henry Cook
9b75dd7e5b Merge branch 'master' into test_mode_reset 2017-09-15 17:26:11 -07:00
Megan Wachs
641a8e7eab test_mode_reset: Correct some gender issues. Tie off signals in the test harness 2017-09-15 16:36:35 -07:00
Henry Cook
e8702e2687 Merge pull request #989 from freechipsproject/config-cleanups 
Clean up various Configs/Fields/Params
 2017-09-15 13:45:15 -07:00
Megan Wachs
6cda4504ac test_mode_reset: use a cleaner interface with bundles and options instead of individual signals 2017-09-15 12:30:39 -07:00
Megan Wachs
ffc514d1bc test_mode_reset: Add missing file 2017-09-14 13:17:37 -07:00
Megan Wachs
a0396b63e8 test_mode_reset: fix one bulk-connect gender issue 2017-09-14 13:16:13 -07:00
Megan Wachs
44edc5fdc3 test_mode_reset: Use simpler apply() method 2017-09-14 13:16:13 -07:00
Megan Wachs
82c00cb656 reset_catch: Allow Test Mode Overrides 2017-09-14 13:16:13 -07:00
Henry Cook
e50d14415e tilelink: more verbose requires 2017-09-13 11:25:42 -07:00
Henry Cook
56dae946b6 coreplex: MemoryBusParams.beatBytes also based on XLen 2017-09-13 11:25:42 -07:00
Henry Cook
b86f4b9bb7 config: use Field defaults over Config defaults 
Also rename some keys that had the same class name as their value's class name.
 2017-09-13 11:25:42 -07:00
Henry Cook
a7540d35b7 ports: use BigInts instead of Longs and the new x"..." context 2017-09-13 11:25:42 -07:00
Henry Cook
37c5af1c0d diplomacy: add x"..." string context 
Enables hex address literals containing underscores.
Converts them to BigInts.
 2017-09-13 11:25:42 -07:00
Henry Cook
063ca0ed4a Merge pull request #983 from freechipsproject/kill-paddrbits 
Remove global fields PAddrBits and ResetVectorBits
 2017-09-11 12:51:10 -07:00
Andrew Waterman
1f606d924f Don't perform in-place correction if there was a recent store (#988) 
Since the correction updates the entire word, the WAW hazard detection
logic is not sufficient to prevent overwriting a recent store.  So,
re-read the word after all pending stores have drained.
 2017-09-08 16:26:54 -07:00
Henry Cook
9c0bfbd500 tile: remove global Field ResetVectorBits 
Reset vector width is determined by systemBus.busView.
Also move some defs from HasCoreParameters to HasTileParameters.
 2017-09-08 14:50:59 -07:00
Henry Cook
3133c321b7 scratchpad: remove dependency on HasCoreParameters 2017-09-08 13:55:40 -07:00
Henry Cook
e46aeb7342 tile: remove PAddrBits in favor of SharedMemoryTLEdge 2017-09-08 13:53:36 -07:00
Wesley W. Terpstra
e7de7f3e82 Merge pull request #985 from freechipsproject/flop-interrupts 
Add Parameters to diplomatic edges
 2017-09-08 13:16:11 -07:00
Andrew Waterman
53dfc5e9be Remove overzealous assertion (#987) 
This assertion made sure the D$ controller was able to write the tag RAM
when a cache line was refilled.  However, it is benign if it fails to do
so: the metadata is invalid at this point, so the miss will simply happen
a second time.

This happens when resolving a tag ECC error during hit-under-miss.
 2017-09-07 18:17:56 -07:00
Wesley W. Terpstra
e723a3f42b MemoryBus: fanout the A for performance 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
6879f5bfb1 tilelink: Xbar now allows for fanout control 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
e831acba9c adapters: support bulk connections 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
06a244f9f9 diplomacy: rename {Left,Right}Star to refer to {Source,Sink}Cardinality 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
bef593c21a diplomacy: edges now capture their Parameters 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
80ed27683e diplomacy: protect against API leakage 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
1365c5f90c diplomacy: implement DisableMonitors scope 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
a450357744 tilelink: Monitor construction method is unconditional 
Whether or not a Monitor should be placed is decided by diplomacy.
 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
7a8364ef08 diplomacy: leverage new Parameters defaults 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
655a08f12e config: support default values for Field[T] keys 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
09d8d476c5 config: require Parameters keys to be Field[T] 
This has been good practice for ages. Enforce it.
 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
42f1ae27fc Xbar: use the IdentityModule to encourage wider fanout 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
5626cdd18f util: add the IdentityModule, useful to dedup wires 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
1a87ed1193 coreplex: add externalSlaveBuffers configuration option 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
fd8a51a910 coreplex: rename externalBuffers to externalMasterBuffers 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
4911a7d44f tilelink Bus: toAsyncSlaves now supports BufferChains 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
040f7e1d49 tilelink: add Bus.toSyncSlaves for easy BufferChain attachment 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
d5c6494f59 tilelink: Bus.toRationalSlaves can have a BufferChain 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
80965e8230 tilelink Buffer: use new :=? adapter API 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
1b705f62f6 diplomacy: support :=? for unknown star inference 2017-09-07 16:03:35 -07:00
Wesley W. Terpstra
6bfea86dbf config: support p.lift(key) to optionally return a value 2017-09-07 16:03:34 -07:00
Wesley W. Terpstra
2d93262f71 RationalCrossing: use ShiftQueues 
These are faster and small don't cost much more.
 2017-09-07 16:03:34 -07:00
Wesley W. Terpstra
50d5d8c1fd ShiftQueue: added a helper object 2017-09-07 16:03:34 -07:00
Wesley W. Terpstra
3e3024c256 ShiftQueue: fix bug in !flow case 2017-09-07 16:03:34 -07:00
Wesley W. Terpstra
ed70b243bd plic: support a configurable number of interrupt register stages 2017-09-07 16:03:34 -07:00
Wesley W. Terpstra
9b55063de6 clint: support a configurable number of interrupt register stages 2017-09-07 16:03:34 -07:00
Megan Wachs
929a924779 Merge pull request #975 from freechipsproject/async_reg 
Cleanup some register primitives
 2017-09-07 13:32:54 -07:00