riscv/rocket-chip
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2085 Commits

Author SHA1 Message Date
Wesley W. Terpstra
2d12ddb4ed tilelink: ToAXI4 makes R channel errors sticky 2017-10-30 21:09:45 -07:00
Wesley W. Terpstra
d6f1612812 tilelink: ToAHB should make read errors sticky as well 2017-10-30 21:09:45 -07:00
Wesley W. Terpstra
4c9d9c6331 tilelink: optimize WidthWidget error circuit to nothing 2017-10-30 21:09:45 -07:00
Wesley W. Terpstra
0992a459be tilelink: Fragmenter should combine errors 2017-10-30 21:09:42 -07:00
Wesley W. Terpstra
13d0bf6808 tilelink: Monitor now enforces spec-defined error rules 2017-10-30 11:27:07 -07:00
Wesley W. Terpstra
a954f020a9 diplomacy: use new node style chaining 2017-10-28 11:34:16 -07:00
Wesley W. Terpstra
6aac658184 diplomacy: convert all helper objects to return nodes 2017-10-28 11:34:16 -07:00
Wesley W. Terpstra
41705808dd Bus: remove deprecated crossing attach methods 2017-10-28 11:34:16 -07:00
Wesley W. Terpstra
7cf5d4aa90 diplomacy: define only primary node types 2017-10-28 11:16:56 -07:00
Wesley W. Terpstra
eeb11a2693 coreplex: eliminate dead code 2017-10-27 01:13:35 -07:00
Wesley W. Terpstra
9f83db998e tile: don't chain too many unneeded TileLink adapters (#1075) 2017-10-27 01:12:58 -07:00
Wesley W. Terpstra
e12bdfdf9b coreplex: attach example external interrupts (#1076) 
Fixes #1071
 2017-10-27 01:12:42 -07:00
Wesley W. Terpstra
13981379c4 CoreplexClockCrossing: add a helper method to decide if a clock is useul (#1074) 2017-10-26 23:39:56 -07:00
Wesley W. Terpstra
1d8e539362 coreplex: confirm crossings actually cross the right boundary 2017-10-26 15:53:01 -07:00
Wesley W. Terpstra
60284082e7 diplomacy: add a hook for injecting code into LazyModule.module scope 2017-10-26 15:19:05 -07:00
Wesley W. Terpstra
a060c37173 diplomacy: expose the API to query a Node for its neighbours 2017-10-26 15:08:06 -07:00
Wesley W. Terpstra
e2d6d4d725 diplomacy: eliminate bindings dead-code 2017-10-26 15:02:21 -07:00
Wesley W. Terpstra
9e33ccdb05 rocket: clarify intent of boundaryBuffers and move to RocketTile 2017-10-26 13:58:52 -07:00
Wesley W. Terpstra
e76e0f6dce interrupts: add debugstring to nodes to show sync depth in graphml 2017-10-26 13:58:52 -07:00
Wesley W. Terpstra
2acff8d21f util: delete old long-deprecated crossing code 2017-10-26 13:58:52 -07:00
Wesley W. Terpstra
da7703aee9 crossings: deprecate non-island crossing style 2017-10-26 13:58:52 -07:00
Wesley W. Terpstra
76df1397e0 crossings: stop using deprecated APIs in tests 2017-10-26 13:04:32 -07:00
Wesley W. Terpstra
380cc6f03b axi4: now also supports the island pattern 2017-10-26 13:04:32 -07:00
Wesley W. Terpstra
05d48d1807 TLBuffer: replace TLBufferChain with TLBuffer.chain 2017-10-26 13:04:32 -07:00
Wesley W. Terpstra
ce2b904b19 coreplex: tidy up interrupt crossings 2017-10-26 13:04:32 -07:00
Wesley W. Terpstra
e30906589f coreplex: refactor crossings to use node pattern 2017-10-26 13:04:32 -07:00
Wesley W. Terpstra
6276ea4291 diplomacy: it possible for NodeHandles to put indirection on their attachment 2017-10-26 13:04:32 -07:00
Wesley W. Terpstra
8c5e8dd071 coreplex: leverage improved := composition 2017-10-26 13:04:32 -07:00
Wesley W. Terpstra
e894d64bca diplomacy: support := composition 
This makes it possible to treat chained composition associatively.
x := y :=? z :=* a ...

It also makes it easy to chain multiple optional adapters:
node :=? (Seq(a, b) ++ c ++ d)
 2017-10-26 13:04:32 -07:00
Henry Cook
b48ab985d0 coreplex: RocketTileWrapper now HasCrossingHelper 2017-10-26 13:04:32 -07:00
Henry Cook
9fe35382ea sbus: tile adapters in sbus scope 2017-10-26 13:04:32 -07:00
Henry Cook
95a2e6ef27 coreplex: improve tile attachment adapters 2017-10-26 13:04:32 -07:00
Wesley W. Terpstra
2175758050 interrupts: implement in crossing wrapper 2017-10-26 13:04:29 -07:00
Wesley W. Terpstra
c6f95570df IntNodes: moved from tilelink to their own package 2017-10-25 16:56:51 -07:00
Wesley W. Terpstra
6bc9c9fc6c coreplex: add a crossing wrapper to generalize the island pattern 2017-10-25 16:56:50 -07:00
Wesley W. Terpstra
7453186b59 diplomacy: add reflection for parent modules to nodes 2017-10-25 16:56:50 -07:00
Christopher Celio
c4978712c9 csr: allow for superscalar decode (#1069) 
* CSR provides a decode port to check for an illegal instruction.
   * This commit now allows for multiple instructions in decode to get this
      illegal instruction information.
   * This commit leverages the existing decodeWidth parameter. This will
      potentially over-provision the number of decode ports needed for
      RVC-enabled cores.

Closes #1068
 2017-10-25 13:58:26 -07:00
Wesley W. Terpstra
82b1aa8116 coreplex: print the A first to look nicer 2017-10-18 16:52:35 -07:00
Wesley W. Terpstra
a1ac23d7ec coreplex: continue to print the device name in the address map 2017-10-18 16:44:53 -07:00
Richard Xia
5a951799aa Add atomics support to DTS JSON file. 2017-10-18 15:17:53 -07:00
Megan Wachs
e9e05b5f3b Add a check that MaxHartIdBits is enough for all hartids (#1054) 
* Add a check that MaxHartIdBits is enough for all hartids

* Correct off-by-one error in hartid check
 2017-10-13 15:20:35 -07:00
Henry Cook
1852ccd8f3 Merge pull request #1053 from freechipsproject/resource-cacheable 
tilelink: cacheable resource permission
 2017-10-12 17:49:49 -07:00
Wesley W. Terpstra
8b58327fa4 axi4: conversion from TL does not need beatBytes (#1051) 
We used to pack the addr_lo into user bits. We don't do that anymore.
There is thus no need to waste those bits, nor to pass that arg.
 2017-10-12 16:41:54 -07:00
Andrew Waterman
21b5367259 Expand C.UNIMP correctly (#1052) 
It was expanding to AMOADD.W, which is clearly not an illegal instruction.
 2017-10-12 14:00:14 -07:00
Henry Cook
ad243ef9f5 tilelink: cacheable resource permission now reports whether a address space could possibly be cached, even if no visible adapters make it so 2017-10-12 13:49:40 -07:00
Henry Cook
ad543e5bb6 Merge pull request #1050 from freechipsproject/uncacheable-tims 
rocket: TIMs should never be cached
 2017-10-12 13:04:00 -07:00
Wesley W. Terpstra
f82e441426 axi4: implement a diplomatic AXI4 clock crossing (#1049) 2017-10-12 00:05:45 -07:00
Henry Cook
66e4bfc2d9 rocket: TIMs should never be cached 2017-10-11 18:22:52 -07:00
Henry Cook
b64609bfe8 Merge pull request #1039 from freechipsproject/tile-crossing-params 
Improvements wrt connecting RocketTiles to SystemBus
 2017-10-11 17:12:03 -07:00
Megan Wachs
7b4c48d005 Correctly hook up the Local Interrupts into the Coreplex. Name some IntXBars 2017-10-11 15:10:50 -07:00