Yunsup Lee
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2c33852c52
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final touches
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2014-09-12 00:19:29 -07:00 |
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Yunsup Lee
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c03c09ec31
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update for rocket-chip release
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2014-08-31 20:26:55 -07:00 |
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Yunsup Lee
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e4b56b5d0e
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generate verilog for rekall
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2014-03-15 15:31:04 -07:00 |
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Yunsup Lee
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5128298e8a
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allow chisel to elaborate Modules outside of the ReferenceChip package
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2014-02-05 03:29:23 -08:00 |
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Stephen Twigg
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e50c5180cd
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Merge branch 'master' into hwacha
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2013-11-14 16:03:55 -08:00 |
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Ben Keller
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c137cf1a46
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Added line to fix race condition in sbt compile; fixed .gitignores
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2013-11-08 15:30:08 -08:00 |
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Stephen Twigg
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7da65434ee
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Initial commit for the hwacha reference-chip/rocket re-integration.
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2013-10-30 20:44:02 -07:00 |
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Andrew Waterman
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3c1d1f7981
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Fix(?) SBT race by defining subproject build order
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2013-10-29 13:27:36 -07:00 |
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Henry Cook
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fc9c676fc1
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add chisel and hardfloat back as sub-projects, bump other sub-projects
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2013-09-26 12:01:46 -07:00 |
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Stephen Twigg
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69daae0dae
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Add dependency resolvers to build.scala to fix build script
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2013-09-05 14:56:41 -07:00 |
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Henry Cook
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b06d33da2f
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Canonicalized sbt, updated makefiles, cleaned up submodules, minor bugfixes
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2013-08-19 19:54:41 -07:00 |
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Henry Cook
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4d916b56e3
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Bump scala to 2.10.2, sbt to 0.13-RC2, including new launcher. Upgrade reflection in network.scala to 2.10 lib. Constants now obtained from subproject package objects. Give network its own file.
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2013-07-24 23:28:43 -07:00 |
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Andrew Waterman
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7330deb13a
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print stack trace if elaboration fails
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2012-11-20 05:39:48 -08:00 |
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Andrew Waterman
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7bcf59a18f
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support continous compilation via "make test"
for c++ emulator only, for now
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2012-11-17 19:58:18 -08:00 |
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Henry Cook
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538b23c223
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Initial version of using sbt tasks to elaborate chisel source and invoke backends' makefiles
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2012-10-23 12:52:59 -07:00 |
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Henry Cook
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17d2bd8926
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Initial version of sbt tasks (elaborate task with no parameters)
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2012-10-23 12:52:00 -07:00 |
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Huy Vo
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24a49350cc
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reference chip design
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2012-10-09 13:05:56 -07:00 |
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Huy Vo
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93a0182b96
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everything to get emulator working
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2012-10-01 19:30:11 -07:00 |
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