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33 Commits

Author SHA1 Message Date
Andrew Waterman 2906c75167 Remove fsim, as it is the same as vsim, modulo CONFIG 2016-08-09 15:42:22 -07:00
Howard Mao 63b814fcd7 only run the important (high coverage) tests in regression suite 2016-08-02 10:54:05 -07:00
Howard Mao d6ba0437ff merge different configs into regression suites to reduce travis build times 2016-06-24 13:02:29 -07:00
Howard Mao 5edb448a1f get rid of slow DualCoreConfig in Travis for now 2016-06-22 16:09:14 -07:00
Howard Mao 82169e971e Dynamically compute number of L1 client channels
Until now, the number of L1 client channels was set statically in the
configuration. This static configuration also assumed the same number of
cached and uncached channels per tile. As we plan to move towards
heterogenous multicore systems, this restriction should be removed.

This commit changes the generator so that number of channels per tile
can be independently set (using cde.Parameters.alterPartial).
The OuterMemorySystem will dynamically compute the number of cached and
uncached channels by summing the number of each kind of channel per core.
2016-06-20 13:02:31 -07:00
Palmer Dabbelt e617bb8aa8 Start testing Chisel 3 in Travis
Now that we have verilator support we can start testing the Chisel 3
Verilog on Travis.  This disables Chisel 2 Travis tests because they're
too slow.
2016-06-15 14:01:22 -07:00
Andrew Waterman da105a5944 Don't allow travis to recurse through submodules 2016-05-25 13:27:49 -07:00
Howard Mao f52fc655a5 remove zscale 2016-05-19 09:43:15 -07:00
Andrew Waterman d0aa4c722d More WIP on new memory map 2016-04-28 16:15:31 -07:00
Howard Mao c5838dd9b3 Fix narrow read/write behavior for AXI converters and fix L2 bugs
Until recently, we were assuming that the data channel in AXI was always
right-justified. However, for narrow writes, the data must actually be
aligned within the byte lanes. This commit changes some of the
converters in order to fix this issue.

There was a bug in the L2 cache in which a merged get request was
causing the tracker to read the old data from the data array,
overwriting the updated data acquired from outer memory. Changed it so
that pending_reads is no longer set if the data in the buffer is already
valid.

There was a bug in the PortedTileLinkCrossbar. The new GrantFromSrc and
FinishToDst types used client_id for routing to managers. This caused
bits to get cut off, which meant the Finish messages could not be routed
correctly. Changed to use manager_id instead.
2016-04-12 15:39:15 -07:00
Howard Mao 5337c7d22d add more complicated memtests to travis 2016-03-31 18:42:14 -07:00
Howard Mao e77900f540 Revert "switch back to Chisel2 for verilog build for now"
This reverts commit 3673365b08.
2016-03-30 19:00:38 -07:00
Howard Mao 3673365b08 switch back to Chisel2 for verilog build for now 2016-03-29 20:16:07 -07:00
Howard Mao 265a82427e add DefaultL2Config and DualCoreConfig to travis 2016-03-29 20:16:07 -07:00
Howard Mao 2b61f28356 don't test DMA controller for now 2016-03-29 20:16:07 -07:00
Palmer Dabbelt 39cf945efb Use Chisel 3 to build verilog on Travis
Chisel 3 can't build the C++ emulator, so we currently can't have direct
support for testing RocketChip.  We can at least test to see if the
Verilog builds when run through Chisel 3, which this patch does.
2016-03-24 12:00:13 -07:00
Albert Magyar a80b0e959d Add support for per-way cache metadata
Adds a new cache parameter (SplitMetadata) and an associated knob.

Closes #62
2016-03-01 13:03:24 -08:00
Howard Mao 8c02cb09ca some additions to Travis and fixes for Testing 2016-02-23 23:37:29 -08:00
Palmer Dabbelt 58d6af207f Cache all the Scala build directories
I hope this will result in Travis building our stuff a lot faster, since this
currently takes about half the time.
2016-02-23 16:47:48 -08:00
Colin Schmidt 1e49eb4958 format .travis.yml (trigger rebuilt to test cache) 2016-02-23 10:58:51 -08:00
Palmer Dabbelt 28c91795c3 Enable travis caching 2016-02-23 10:58:51 -08:00
Palmer Dabbelt edd0b3b824 Move travis to the regression Makefile
We want to add support for caching riscv-tools builds on Travis and the easiest
way to do so looks like to jus go ahead and use
2016-02-23 10:58:51 -08:00
Colin Schmidt c1b5f71ee7 don't run bmarks in parallel 2016-02-22 13:34:24 -08:00
Colin Schmidt 43c2237ef7 add more memtest configs and remove channel test 2016-02-22 09:38:44 -08:00
Colin Schmidt e4c4a90648 add a config to travis for memchannel mux select 2016-02-22 09:36:53 -08:00
Colin Schmidt 3dae576c9e add travis configs for memtest 2016-02-22 09:36:53 -08:00
Colin Schmidt c944193e16 add dma configs to travis 2016-02-02 16:06:01 -08:00
Colin Schmidt ec4ade988b [travis] add multiple configs including rocc 2015-11-28 07:17:49 -08:00
Colin Schmidt 7ecb936bf5 Remove -j from "make run-bmark-tests" in travis
+currently causes inconsistency in build success
+unclear what root cause is
2015-09-16 12:27:05 -07:00
Christopher Celio 754c47bdd1 Removed "make debug" test from travis
- currently causes gcc4.8 to crash
  - likely due to high memory requirements in compiling generated c++
    code for debug/vcd output
2015-09-14 15:45:50 -07:00
Christopher Celio 17e971bbfa Add emulator "make debug" and "-j" to travis 2015-09-10 17:34:16 -07:00
Colin Schmidt af7336ef8b blacklist private branches from travis 2015-09-08 15:13:38 -07:00
Scott Beamer b88c283b21 add travis support and tests 2015-08-25 13:29:20 -07:00