riscv/rocket-chip
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Author SHA1 Message Date
mwachs5andAndrew Waterman 22ffe36258 Add a queue for timing QoR between L2->MMIO network (#217) 2016-08-19 22:51:49 -07:00
Megan Wachs 55c992bb3a Use FoldRight() instead of for loop 2016-08-01 16:56:33 -07:00
Megan Wachs 8db2e8829f Allow aggregate CONFIG on Command Line 2016-08-01 14:24:16 -07:00
mwachs5andAndrew Waterman 4465260469 Update README.md 
- List things that are no longer submodules as subpackages instead
- clean up some formatting issues
 2016-07-29 17:56:42 -07:00
Megan WachsandHoward Mao c31c650def If NTiles == 1, only use MEI. Also Create configuration for ManagerToClientStatelessBridge. 2016-07-21 13:54:28 -07:00
Megan WachsandHoward Mao eb9e998c08 Add ManagerToClientStatelessBridge 2016-07-21 13:49:16 -07:00
mwachs5andAndrew Waterman cff8de9814 Use new Mul/Div parameters vs UseFastMulDiv (#48) 
* Use new Mul/Div parameters vs UseFastMulDiv

* Rename MulDivUnroll to MulUnroll
 2016-07-15 15:41:20 -07:00
Megan Wachs 407bc95c42 Rename MulDivUnroll to MulUnroll 2016-07-15 15:40:17 -07:00
Megan Wachs 4c26a6bc96 Create seperate Mul/Div paramters instead of UseFastMulDiv 2016-07-15 14:40:37 -07:00
mwachs5andAndrew Waterman 36720d915a Update README.md (#161) 
Correct typo in heading
 2016-07-11 00:34:13 -07:00
mwachs5andAndrew Waterman 2d2096e509 Add smaller ROM/RAM for 32-bit debug (#60) 2016-06-15 15:07:43 -07:00
Megan WachsandAndrew Waterman cee0cf345e [debug] Update Debug ROM contents to write F..F to RAM in case of exception 2016-06-09 14:05:30 -07:00
mwachs5andAndrew Waterman 93c1b17b52 [debug] Remove erroneous buffer on SB read data (#56) 2016-06-08 23:31:13 -04:00
Megan WachsandAndrew Waterman b832689642 Correct Debug ROM contents 2016-06-05 19:35:25 -07:00
Megan WachsandAndrew Waterman 605fb5b92f [debug]: fix issue with subword select logic 2016-06-05 19:31:07 -07:00
Megan WachsandAndrew Waterman 3e8322816b Correct DMINFO Fields 2016-06-05 19:29:50 -07:00
Megan WachsandAndrew Waterman 7e550ab07c [debug] rocket: fix for issue 121, correct debug ROM and stall logic 2016-06-05 19:29:44 -07:00
mwachs5andAndrew Waterman 740a6073f6 Add Debug Module (#49) 
* Add Debug Module

* [debug] Remove unit tests, update System Bus register addresses, parameterize nComponents

* [debug] Update Debug ROM contents to match updated addresses
 2016-06-01 16:33:33 -07:00
mwachs5 a81334f505 Update README links to point to this repo 2016-04-06 14:10:04 -07:00
mwachs5andHenry Cook 22e7b3ff2f Update README.md 
- adding instructions of how to run with groundtest
- correct some MD syntax in README
- add some spaces
- minor changes to wording
- remove spurious 'class'
- add commands for running w/ TraceGenConfig
- add code from http://www.cl.cam.ac.uk/~mn416/tracegen.html
- Update README.md
- add WSO note
- correct some syntax within the code blocks and add note about run-asm-tests, run-bmark-tests
- Add one more command to the "quick reference" to show the complete flow
- Correct WSO to WMO
- Add information about tracegen+check.sh
- Use tracegen.py commands instead of running the emulator directly
- added a missing newline
- remove extra head command
 2016-03-31 14:20:14 -07:00