riscv/rocket-chip
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Author SHA1 Message Date
Megan Wachs
eae4fe1469 plic: Recode to use the knowledge that only one interrupt can be claimed at a time. 2017-06-29 19:09:57 -07:00
Wesley W. Terpstra
e3c7bb3b1f SRAM: MemoryDevices use .reg (not .reg("mem")) (#835) 2017-06-29 19:07:12 -07:00
Megan Wachs
ae6971b6db Merge pull request #834 from freechipsproject/resumereq-race 
debug: Fix race between resumereq and resumeack
 2017-06-29 13:38:20 -07:00
Megan Wachs
0668f13d99 debug: Fix race between resumereq and resumeack 
For an arbitrary DMI master on a fast clock running against a core
on a slow clock, there was a race between writing resumereq and
reading resumeack. When using JTAG DTM this does not occur in practice,
but clean it up for running simulations with FESVR and future DMI masters.
 2017-06-29 12:27:23 -07:00
Wesley W. Terpstra
7dae3388e1 Merge pull request #830 from freechipsproject/flip-dts-idtim 
Flip dts itim and dtim references
 2017-06-29 00:18:19 -07:00
Wesley W. Terpstra
5edc4546e3 rocket: add dtim and itim refs to cpus 2017-06-28 23:10:58 -07:00
Wesley W. Terpstra
7d6f8d48f2 Revert "rocket: link dtim to its cpu" 
This reverts commit e6c2d446cc.
 2017-06-28 23:10:57 -07:00
Wesley W. Terpstra
fbcd6f0eb2 Revert "rocket: link itim to its cpu" 
This reverts commit 48390ed604.
 2017-06-28 23:10:57 -07:00
Henry Cook
6e5a4c687f diplomacy: a type of connect that always disables monitors (#828) 2017-06-28 21:48:10 -07:00
Megan Wachs
992b480c74 Merge pull request #825 from freechipsproject/debug_wfi 
Debug + WFI Interactions
 2017-06-28 21:28:51 -07:00
Wesley W. Terpstra
5002d2accf Merge pull request #827 from freechipsproject/dts-improvements 
Dts improvements
 2017-06-28 17:45:06 -07:00
Megan Wachs
39b06a917f bump riscv-tools for fesvr-dont-die 2017-06-28 16:38:02 -07:00
Wesley W. Terpstra
66489ffa13 rom+sram: add a compatible field 2017-06-28 15:41:20 -07:00
Wesley W. Terpstra
ca3030cba3 dcache: fix a gender inversion bug introduced in #826 2017-06-28 15:38:53 -07:00
Wesley W. Terpstra
02aa80a958 TLZero: include a version number 2017-06-28 15:12:46 -07:00
Wesley W. Terpstra
48390ed604 rocket: link itim to its cpu 2017-06-28 15:06:19 -07:00
Wesley W. Terpstra
e6c2d446cc rocket: link dtim to its cpu 2017-06-28 15:06:19 -07:00
Wesley W. Terpstra
3f6d5110cd rocket: dtim is not a dcache 2017-06-28 15:06:19 -07:00
Wesley W. Terpstra
bca3db0866 diplomacy: add RWXC permissions also to ResourceMappings 2017-06-28 15:06:19 -07:00
Wesley W. Terpstra
5436be54ff periphery: use SimpleBus for mmio ports 2017-06-28 15:06:19 -07:00
Wesley W. Terpstra
171e1a4c05 diplomacy: add SimpleBus to describe bridges 2017-06-28 15:06:19 -07:00
Wesley W. Terpstra
84dc23c215 devices: add reg-names to most devices 2017-06-28 15:06:16 -07:00
Wesley W. Terpstra
0bf46edb6c diplomacy: support reg-names in DTS output 2017-06-28 14:26:55 -07:00
Wesley W. Terpstra
852f03282f rocket: give itim and dtim a compatible field for drivers to match 2017-06-28 14:26:55 -07:00
Wesley W. Terpstra
6c2b770605 plic: do not output #address-cells 
This is only needed for an interrupt-map, not an interrupt-controller.
 2017-06-28 14:26:55 -07:00
Andrew Waterman
936096dd42 Merge pull request #826 from freechipsproject/tlb2 
Various memory system improvements
 2017-06-28 13:51:24 -07:00
Megan Wachs
35b89d8023 bump riscv-tools for fesvr-don't-die 2017-06-28 13:36:53 -07:00
Andrew Waterman
b9a934ae28 Support eccBytes > 1 2017-06-28 02:09:18 -07:00
Andrew Waterman
8e4be40efc Propagate wb_reg_rs2 for sfence ASID 
This would have been a bug if we supported ASIDs.
 2017-06-28 02:09:18 -07:00
Andrew Waterman
2077e4190b Make log more sensible for long-latency operations 
Show only one write to the destination register, not two.
 2017-06-28 02:09:18 -07:00
Andrew Waterman
6f8fdff762 Basic L1 D$ ECC support 
Only supports ECC on data, not tags; only supports byte granularity.
 2017-06-28 02:09:18 -07:00
Andrew Waterman
6100600179 Minor D$ code cleanup 2017-06-28 02:09:18 -07:00
Andrew Waterman
9c78ac4d78 Add grouped method to AugmentedUInt, like Seq.grouped 2017-06-28 02:09:18 -07:00
Andrew Waterman
8989f5654c Add swizzle method to Encoding 2017-06-28 02:09:18 -07:00
Andrew Waterman
3e04a99f61 Refactor frontend exception passing 
Bundle them, and leverage regularity, so that if we have to add more
exceptions in the future, we don't need to change so much code.
 2017-06-28 02:09:18 -07:00
Andrew Waterman
cc2f87c214 Forbid S-mode execution from user memory 
285c81746f
 2017-06-28 02:09:18 -07:00
Andrew Waterman
8aa16a11f3 Reduce D$ access energy when refill width > access width 2017-06-28 02:09:18 -07:00
Andrew Waterman
25f585f2a9 Remove unused signal from TLB interface 2017-06-28 02:09:18 -07:00
Andrew Waterman
d5f80df0ae Allow speculative I$ refill to cacheable regions 
Backpedaling on 27b143013f.  Shaving
four cycles off of I$ miss penalty is obviously worth the HW cost.
 2017-06-28 02:09:18 -07:00
Megan Wachs
3fc75c2714 debug: report UNSUPPORTED more consistently. Allow haltreq/resumereq to be R as well as W. 2017-06-27 17:40:58 -07:00
Megan Wachs
e1fe0f245b debug: Don't reset debugint register, as none of the interrupt registers are. 2017-06-27 14:10:13 -07:00
Megan Wachs
136e4b6c27 debug: use consistent coding style (Reg(init ... ) vs RegInit) 2017-06-27 13:42:38 -07:00
Megan Wachs
3b9550ede3 debug: correctly declare reg_debugint 2017-06-27 13:42:38 -07:00
Megan Wachs
56839b2c62 debug: Remove DebugInterrupt from DCSR (it is no longer part of V13 spec) 2017-06-27 13:42:38 -07:00
Megan Wachs
665c2a349c Correct Debug + WFI Interactions 
1) Debug interrupt should end WFI
2) WFI should end immedately during single-step
3) WFI should act like NOP during Debug Mode
 2017-06-27 13:42:38 -07:00
Zihao Yu
c9cfe46604 rocket,Rocket: fix type mismatch (#819) 2017-06-27 11:22:08 -07:00
Jack Koenig
8d07d0af38 Merge pull request #820 from freechipsproject/bump-firrtl 
Bump firrtl to get constant propagation improvements
 2017-06-26 18:47:50 -07:00
Wesley W. Terpstra
66f64a9759 tilelink2 ToAXI4: don't interlock R+W for non-FIFO masters (#822) 
idCount <= 1 implies that no more than one transaction can be inflight,
so there is no need to interlock R+W. However, when stripBits > 0, it is
possible for a non-FIFO master to have > 1 idCount. In this case, we
also don't need to interlock R+W.
 2017-06-26 17:54:17 -07:00
Jack
e461e0f796 Bump firrtl to get constant propagation improvements 2017-06-26 17:18:52 -07:00
Andrew Waterman
72c46e6c05 Merge pull request #818 from sashimi-yzh/faster-verilator-compile 
emulator,Makefile-verilator: add --output-split-cfuncs flag
 2017-06-26 11:39:42 -07:00