Andrew Waterman
176110b6d3
Don't trigger ECC writebacks when a release is in flight
2017-08-12 15:23:57 -07:00
Andrew Waterman
809c7e8551
Don't merge stores that manifest WAW hazards
...
The following sequence would drop the first store when eccBytes=4:
sb x0, 0(t0)
nop
sb x0, 4(t0)
nop
sb x0, 1(t0)
Because the first and second store are to different ECC granules, the
hazard check correctly allowed the second one to proceed, but the third
was merged with the second, even though it conflicted with the first.
So, don't allow the third to be merged with the second, since the second
stored to a different ECC granule.
2017-08-08 15:19:05 -07:00
Andrew Waterman
82e13443b2
Merge pull request #937 from freechipsproject/critical-paths
...
Perform tag error detectoin/correction in same cycle as RAM
2017-08-08 15:03:28 -07:00
Andrew Waterman
7935c61c19
Don't report to the DTIM that data is cacheable
...
Otherwise, it will attempt to perform AMOs where they're unsupported!
2017-08-08 11:55:04 -07:00
Andrew Waterman
74d309c18e
Make I vs. D a static property of TLB, not an input pin
...
The microarchitecture doesn't really support unified TLBs, so don't fake it.
2017-08-08 11:54:47 -07:00
Andrew Waterman
e92981b0bd
DRY
2017-08-08 11:46:38 -07:00
Andrew Waterman
62ccba304c
Perform tag error detectoin/correction in same cycle as RAM
...
The tag RAMs tend to be fast, so take up some of the slack.
This makes s2_nack faster.
2017-08-08 10:21:30 -07:00
Andrew Waterman
402907990c
Revert "Remove one gate from D$ ECC check"
...
This reverts commit 7d94074b05
, which
works fine with optimistic behavioral RAMs but not real ones.
2017-08-07 17:33:20 -07:00
Andrew Waterman
7d94074b05
Remove one gate from D$ ECC check
...
The D$ corrects via writeback, so which word the error was in doesn't
matter, as the entire line is corrected.
2017-08-06 17:36:53 -07:00
Andrew Waterman
83875e3a0c
Only flush D$ on FENCE.I if it won't always be probed on I$ miss
2017-08-05 14:22:40 -07:00
Andrew Waterman
991e16de92
Remove probe address mux from TLB response path
2017-08-05 12:57:38 -07:00
Andrew Waterman
2eb239d03f
Add option to retime D$ way mux into subsequent pipeline stage
2017-08-01 23:59:20 -07:00
Andrew Waterman
2ecea2ef60
Don't use a pipe queue on D$ TL A-channel
...
This cuts an I$->D$ path.
2017-08-01 15:17:07 -07:00
Andrew Waterman
5681693ccc
Fix a D$ ready-valid signaling regression
...
I broke this in 66d06460fa
.
2017-07-31 18:05:14 -07:00
Henry Cook
11332c1226
dcache: break potential combinatorial loop by making pstore_drain_on_miss more conservative
2017-07-31 14:03:30 -07:00
Andrew Waterman
ac4339a8e7
Pass D$ backpressure to D-channel, rather than asserting
2017-07-29 11:48:36 -07:00
Andrew Waterman
edcd2c696c
Avoid needless stall on E-channel back pressure
2017-07-29 11:47:58 -07:00
Andrew Waterman
2e8b02e780
Merge D$ store hits when ECC is enabled
...
This avoids pipeline flushes due to subword WAW hazards, as with
consecutive byte stores.
2017-07-28 12:56:36 -07:00
Andrew Waterman
838864870e
Bypass TLB refill signal to halve L2 TLB hit time
...
The 4-cycle hit time is 1 cycle too long to avoid a second
pipeline replay, so it was effectively 9 cycles instead of 4.
2017-07-28 12:56:36 -07:00
Andrew Waterman
ae1f7a95f6
Don't nack misses when there's a pending store
...
That effectively increased the miss latency by 5 cycles when there was
a store hit followed by a load miss. Since pending stores are drained
when releaseInFlight, the check I removed was redundant.
2017-07-28 12:56:36 -07:00
Andrew Waterman
66d06460fa
Add option for acquire-before-release
2017-07-25 15:19:16 -07:00
Henry Cook
4c595d175c
Refactor package hierarchy and remove legacy bus protocol implementations ( #845 )
...
* Refactors package hierarchy.
Additionally:
- Removes legacy ground tests and configs
- Removes legacy bus protocol implementations
- Removes NTiles
- Adds devices package
- Adds more functions to util package
2017-07-07 10:48:16 -07:00
Andrew Waterman
be4eceec0d
Fix stupid D$ probe bug
2017-07-06 01:20:47 -07:00
Andrew Waterman
90a7d6a343
Add L2 TLB option
2017-07-06 01:19:18 -07:00
Andrew Waterman
0ef45fac9b
Add tag ECC to D$
2017-07-03 18:16:37 -07:00
Andrew Waterman
e9752f76ae
Improve probe state machine
...
- Reduce reliance on s2_prb_ack_data due to future ECC changes
- Shave a cycle off valid, but clean, probes
- Code cleanup
2017-07-03 16:25:04 -07:00
Richard Xia
5b46350bc3
Make sure that DCache s2_xcpt data scratchpad case is assigned to after initial assignment.
2017-06-30 17:44:16 -07:00
Wesley W. Terpstra
ca3030cba3
dcache: fix a gender inversion bug introduced in #826
2017-06-28 15:38:53 -07:00
Andrew Waterman
b9a934ae28
Support eccBytes > 1
2017-06-28 02:09:18 -07:00
Andrew Waterman
6f8fdff762
Basic L1 D$ ECC support
...
Only supports ECC on data, not tags; only supports byte granularity.
2017-06-28 02:09:18 -07:00
Andrew Waterman
6100600179
Minor D$ code cleanup
2017-06-28 02:09:18 -07:00
Andrew Waterman
8aa16a11f3
Reduce D$ access energy when refill width > access width
2017-06-28 02:09:18 -07:00
Andrew Waterman
25f585f2a9
Remove unused signal from TLB interface
2017-06-28 02:09:18 -07:00
Henry Cook
6b79842e66
dcache: just left shift by untagbits to get tag
...
Always safe because of the requirement on coreplex/RocketTiles.scala:126
2017-06-20 16:35:28 -07:00
Wesley W. Terpstra
80c63c0da6
rocket: include hartid in cache master names
2017-06-02 15:52:23 -07:00
Andrew Waterman
dbc5e7c494
Add TLB miss performance counters ( #762 )
2017-05-23 12:52:25 -07:00
Andrew Waterman
b2b4c1abcd
Separate tag ECC and data ECC options ( #761 )
2017-05-23 12:51:48 -07:00
Andrew Waterman
3a1a37d41b
Support PutPartial in ScratchpadSlavePort
2017-05-02 03:07:02 -07:00
Andrew Waterman
f8151ce786
Remove subword load muxing in ScratchpadSlavePort
2017-05-02 00:14:46 -07:00
Andrew Waterman
8fd5ecdff8
Set io.cpu.resp.bits.addr for MMIO loads without affecting QoR
2017-04-27 19:50:38 -07:00
Andrew Waterman
80d826b94a
Make DTIM deduplicatable
2017-04-26 19:35:35 -07:00
Wesley W. Terpstra
f3ab23d068
dcache: fix stupidly wrong crossing comparison ( #703 )
2017-04-25 09:18:41 -07:00
Wesley W. Terpstra
4807ce7ced
dcache: put a flow Q to absorb back-pressure without restarting pipeline ( #701 )
...
* dcache: put a flow Q to absorb back-pressure without restarting pipeline
When used with a RationalCrossing, pipelined MMIO does not come out cleanly.
The first beat works, but if the second beat gets stalled, the pipeline is
restarted. This is a quick hacky test to absorb the beats. Perhaps a better
fix can be made to achieve the same effect.
* dcache: provision as few stages as possible
2017-04-24 23:28:04 -07:00
Andrew Waterman
d82a0dc231
Mitigate D$ exception critical path, yet again
2017-04-18 00:47:58 -07:00
Andrew Waterman
c99ce7ce5d
Only report D$ exceptions on not-nacked accesses
2017-04-18 00:47:58 -07:00
Andrew Waterman
6de6f38894
Pipeline D$ exception response into s2
2017-04-18 00:47:58 -07:00
Andrew Waterman
cc9ec1d51a
Send D$ grant acks early; accept release acks early
...
We now need to block the B-channel for a few cycles after a grant to
allow the processor to get at least one request through, preventing
livelock.
2017-04-18 00:47:58 -07:00
Andrew Waterman
c366007a0d
Tighten PMAs for LR/SC and misaligned accesses
...
- LR/SC on cacheable memory only (not even scratchpad)
- No misaligned accesses on regions with get/put-effects
2017-04-18 00:47:58 -07:00
Andrew Waterman
7871ec82c4
Guarantee probe forward progress during LR storm
2017-04-18 00:47:58 -07:00
Andrew Waterman
d203c4c654
Check AMO operation legality in TLB
2017-04-14 01:03:11 -07:00