riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
622 Commits 1 Branch 0 Tags
11b3cee07a6ddf8414409f85b98ea98ae93e8818
Commit Graph
5 Commits
This Branch
This Branch
All Branches
Author SHA1 Message Date
Wesley W. TerpstraandAndrew Waterman 11b3cee07a Ahb tweaks (#50) 
* ahb: handle tlDataBytes==1 and tlDataBeats==1 gracefully

I only now learned that chisel does not handle 0-width wires properly
and that log2Up and log2Ceil differ on 1. Fix-up code to handle this.

* ahb: optionally disable atomics => optimize to nothing

Trust the compiler the compiler to optimize away unused logic.
 2016-06-01 16:42:39 -07:00
Wesley W. TerpstraandAndrew Waterman 7f1792cba3 ahb: backport bridge to chisel2 
Closes #47
 2016-05-25 13:40:24 -07:00
Wesley W. Terpstra a012341d96 ahb: TileLink => AHB bridge, including atomics and bursts 2016-05-24 14:58:27 -07:00
Wesley W. Terpstra ace9362d81 ahb: amoalu does not need so many parameters! (i want to reuse it) 2016-05-24 14:58:27 -07:00
Wesley W. Terpstra 00d31dc5c5 bram: use new hasti definitions 2016-05-24 13:35:16 -07:00