This removes the mostly obsolete 'numIn/Out' range restrictions on nodes.
It also makes it possible to connect optional crossbars that disappear.
val x = TLXbar()
x := master
slave := x
val y = TLXbar()
x :=* y // only connect y if it gets used
This will create crossbar x, but crossbar y will disappear.
When passed a Wire, WNotify outputs that wire on reads wire => d_bits.
Furthermore, it updates the Wire when a write occures d_ready => wire.
These registers should be returning undefined value on read, anyway.
...instead of on the master side of the system bus.
People inheriting from HasTileMasterPort might need to add
`masterNode := tileBus.node` to their Tile child class.
* debug: Update macros from spec
* debug: some corrections in the auto-generated files
* debug: update renamed fields
* Debug: implement the implicit ebreak option for small program buffers
* debug: clean up some unused code and add more require() explanations
* debug: make implicit ebreak false
* debug: Add the havereset/haveresetack functionality
* debug: program buffer can still be 16 even if there is an implicit ebreak
When switching ports, the bypass stalls new messages until all
outstanding messages have received their responses. However, this
stall must NOT stop the remaining beats of a partially sent request.
* JTAG: Use sorted map for stability
Otherwise the generated FIRRTL/Verilog is non deterministic
* jtag : parens for clarity
* jtag: Use deterministic ListMap and sort for stability
* JTAG: use slightly clearer SortedMap (clearer to me anyway)
* jtag: whitespace cleanup
* CacheCork: an error Grant still says 'toT' even though it is transient
Grants with errors must be handled by a client as though no actual
permissions were obtained, so that two clients do not both end up believing
that they own a block which is only temporarily offline. However, the
Grant MESSAGE should still match the request; ie. if you did Acquire.NtoT,
the response must be Grant.toT, even though the 'error' bit signals that
the Grant actually grants no permissions.
This keeps the implementation of request-response tracking in interstitial
adapters and FSMs simple, consistent with the way multibeat errors must
include all their beats.
* Error: handle permissions properly
