Andrew Waterman
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128ec567ed
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make BTB fully associative; don't use it for JALR
JALR created a long path from the ALU in execute stage
to an address comparator to the next-PC mux. the benfit
was close to nil, anyway.
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2012-02-09 01:34:00 -08:00 |
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Andrew Waterman
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01a156eb98
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make # of dcache lines configurable
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2012-02-01 21:11:45 -08:00 |
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Henry Cook
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c5a4eaa0a1
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Associative cache, boots kernel
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2012-02-01 13:26:04 -08:00 |
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Andrew Waterman
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97c379f1d7
|
made I$ associative
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2012-01-24 16:51:30 -08:00 |
|
Henry Cook
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8766438bb9
|
Updated chisel removes ^^ from language. Removed from rocket source, updated jar.
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2012-01-23 17:09:23 -08:00 |
|
Henry Cook
|
7e25749581
|
Groundwork for assoc cache implementation
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2012-01-18 17:09:35 -08:00 |
|
Andrew Waterman
|
07f184df2f
|
adhere to new chisel c naming convention
|
2012-01-18 15:23:21 -08:00 |
|
Andrew Waterman
|
4807d7222b
|
use replay to handle I$ misses
this eliminates a long path in the fetch stage
|
2012-01-11 19:20:20 -08:00 |
|
Andrew Waterman
|
8308345364
|
work in progress on hellacache
|
2011-12-10 07:01:47 -08:00 |
|
Rimas Avizienis
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e894b79870
|
caches now use Mem4() memories for tag+data arrays
|
2011-12-03 19:41:15 -08:00 |
|
Rimas Avizienis
|
e96430d862
|
integrating ITLB & PTW
|
2011-11-09 14:52:17 -08:00 |
|
Rimas Avizienis
|
c06e2d16e4
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initial commit of rocket chisel project, riscv assembly tests and benchmarks
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2011-10-25 23:02:47 -07:00 |
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