Wesley W. Terpstra
5efd38bf97
apb: put both aFlow options under regression
2017-03-16 15:36:14 -07:00
Wesley W. Terpstra
882a7ff8ff
TLToAPB: use the now standard aFlow parameter name
2017-03-16 15:34:59 -07:00
Wesley W. Terpstra
e31b84af33
axi4: use common BufferParams
2017-03-16 15:32:17 -07:00
Wesley W. Terpstra
ca2c709d29
TLBuffer: move TLBufferParams to diplomacy.BufferParams
2017-03-16 15:19:36 -07:00
Wesley W. Terpstra
778c8a5c97
ToAHB: appease AHB VIP
2017-03-16 15:17:05 -07:00
Wesley W. Terpstra
963d244094
unittest: try both aFlow settings of TLToAHB
2017-03-16 15:13:57 -07:00
Wesley W. Terpstra
604a164b97
TLToAHB: rename parameter to aFlow
2017-03-16 15:10:54 -07:00
Wesley W. Terpstra
bb49575368
ahb: rewrote TLToAHB to avoid retracting requests on stall
2017-03-16 14:36:30 -07:00
Henry Cook
4f5f686c7e
bump riscv-tools ( #586 )
2017-03-15 18:09:26 -07:00
Wesley W. Terpstra
625919722c
Merge pull request #584 from ucb-bar/ahb-in
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AHB master port support
2017-03-14 19:28:09 -07:00
Wesley W. Terpstra
c95c2ca9c8
AHB: include bridge unit tests
2017-03-14 18:34:21 -07:00
Wesley W. Terpstra
0c5fd76089
ahb: implement a ToTL bridge
2017-03-14 18:34:17 -07:00
Wesley W. Terpstra
7f71df0925
apb: better test coverage
2017-03-14 18:34:17 -07:00
Wesley W. Terpstra
5885bf29b5
axi4: improve test harness
2017-03-14 18:34:17 -07:00
Wesley W. Terpstra
d98fd942f1
tilelink2: optimize the supportsX check circuits
2017-03-14 18:34:17 -07:00
Wesley W. Terpstra
3c5c877409
tilelink2: make TLBuffer API more flexible
2017-03-14 14:06:18 -07:00
Wesley W. Terpstra
6fc3ec3d63
tileink2: add a TestRAM; a zero-delay RAM useful for testing
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TLRAM always answers after 1 cycle. We need a RAM that answers in 0.
2017-03-14 14:06:17 -07:00
Henry Cook
e9c694522b
Merge pull request #578 from ucb-bar/priv-1.10
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Privileged architecture updates
2017-03-14 13:20:19 -07:00
Henry Cook
bb0390630c
Merge branch 'master' into priv-1.10
2017-03-13 21:40:12 -07:00
Leway Colin
1322a02637
Fixed Hasti can't handle N masters to one slave #571 ( #576 )
2017-03-13 20:36:53 -07:00
Henry Cook
4eb261c895
Merge pull request #582 from ucb-bar/more-fuzzing
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Fuzzer enhancements
2017-03-13 15:31:51 -07:00
Andrew Waterman
d6f571cbbb
Implement mstatus.TSR
2017-03-13 14:50:06 -07:00
Andrew Waterman
1fea0460ba
Support superpage entries in TLB
2017-03-13 14:50:06 -07:00
Andrew Waterman
2d267b4940
Support corner cases in TLBPermissions
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Don't crap out if the yes-set or no-set is empty.
2017-03-13 14:50:06 -07:00
Andrew Waterman
90b5cc96cb
Gracefully handle empty ports in AddressDecoder
2017-03-13 14:50:06 -07:00
Wesley W. Terpstra
c847559853
TLB: add a helper API to determine homogeneous page permissions
2017-03-13 14:50:06 -07:00
Wesley W. Terpstra
eaf474a081
LFSR: use random intial value of the start register
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We just need to make sure it doesn't initialize randomly stuck at 0.
2017-03-13 13:17:52 -07:00
Henry Cook
fe287864ef
bump firrtl
2017-03-13 13:14:16 -07:00
Henry Cook
1a3fec61c0
Merge branch 'master' into priv-1.10
2017-03-13 11:59:18 -07:00
Wesley W. Terpstra
d2da33e4b1
Fuzzer: use different LFSR seeds based on simulator seed
2017-03-11 02:53:43 -08:00
Wesley W. Terpstra
bb6108abd5
Tests: include more random delays
2017-03-11 02:53:43 -08:00
Wesley W. Terpstra
0c7fb87390
TLDelayer: insert noise on invalid cycles
2017-03-11 02:53:43 -08:00
Jacob Chang
1c6dde8c15
Make parameters for TLToAHB and TLToAXI4 accessable ( #581 )
2017-03-10 22:26:38 -08:00
Henry Cook
dbc8f4b30b
last => done
2017-03-10 15:58:38 -08:00
Andrew Waterman
380c10f7bd
Zap conflicting TLB entries, preparing for superpage support
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Superpages create the possibility that two entries in the TLB may match.
This corresponds to a software bug, but we can't return complete garbage;
we must return either the old translation or the new translation. This
isn't compatible with the Mux1H approach. So, flush the TLB and report
a miss on duplicate entries.
2017-03-10 15:58:23 -08:00
Andrew Waterman
b24c43badb
Don't double-count release traffic in perfctrs
2017-03-09 16:49:02 -08:00
Andrew Waterman
63f8ce36f6
Avoid VM exceptions in groundtest by setting Accessed bit
2017-03-09 16:48:28 -08:00
Andrew Waterman
4f8f05d635
Add performance counter facility
2017-03-09 13:58:50 -08:00
Andrew Waterman
e57ee2692d
bump tools
2017-03-09 13:58:40 -08:00
Andrew Waterman
33b6d48376
Fix haltnot reporting (previously always returned 0)
2017-03-09 13:58:40 -08:00
Andrew Waterman
24a2278fc4
Perform all illegal-instruction detection in ID stage
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This is simpler, reduces what would have become a critical path in
the commit stage, and will make it easier to support the mbadinst
CSR if it is implemented.
2017-03-09 11:29:51 -08:00
Andrew Waterman
7668827741
Support unrolling the integer divider
2017-03-09 11:29:51 -08:00
Andrew Waterman
74d8d672bf
Improve BTB critical path at slight accuracy cost
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Make entries fully associative on lower 14 bits only, not full address.
2017-03-09 11:29:51 -08:00
Andrew Waterman
11c8857b5d
Don't re-read I$ RAMs on stall
2017-03-09 11:29:51 -08:00
Andrew Waterman
db0a02b78e
WIP on priv-1.10
2017-03-09 11:29:51 -08:00
Wesley W. Terpstra
43dea38ee9
dcache: we need the bits within the beat so select the right word ( #575 )
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We now have confirmation that it fixed the problem.
2017-03-08 00:19:09 -08:00
Andrew Waterman
603b8af2eb
Don't canonicalize 32-bit FP results in the various pipelines
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It's redundant with the new scheme, so just adds HW for no reason.
2017-03-07 20:51:32 -08:00
Andrew Waterman
f505aba1ac
Use sNaN value for flw, like other single-precision ops
2017-03-07 20:51:32 -08:00
Andrew Waterman
cc389bea90
Fix in-register representation of fdiv.s/fsqrt.s result
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We were zero-extending it, which is a double-precision zero in the recoded
format. So, when spilled and reloaded with fsd/fld, the original value
was destroyed. Instead, set the MSBs so that it represents sNaN. When
spilled, the single-precision number will be preserved as the NaN payload.
2017-03-07 20:51:32 -08:00
Henry Cook
4af437fdab
RANDOMIZE_MEM_INIT vlsi_mem_gen ( #572 )
2017-03-07 01:56:15 -08:00
