020fbe8be9
diplomacy: make config.Parameters available in bundle connect()
...
This makes it posisble to use Parameters to control Monitors.
However, we need to make all LazyModules carry Parameters.
2016-12-07 12:24:01 -08:00
f3d0692619
Make a directory for the config package ( #464 )
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* [config] make dir structure mirror packages
* [config] expunge max_int
2016-12-05 10:42:16 -08:00
b7963eca4e
copyright: ran scripts/modify-copyright
2016-11-27 22:15:43 -08:00
a17753983a
coreplex: allow legacy devices to override the config string ( #458 )
2016-11-25 19:38:24 -08:00
2b80386a9e
rocketchip: TileInterrupts needs a TLCacheEdge ( #456 )
2016-11-25 17:02:29 -08:00
0baa1c9a45
coreplex: CacheBlockOffsetBits was wrong!
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This bug is ancient. I don't understand how it never mattered before.
Anyway, in processors with a custom CacheBlockBytes, this value is wrong!
The symptom is that TL1 components end up missing high address bits.
This causes, for example, a system to jump to 0 instead of RAM.
I don't understand how this very serious bug did not cause problems before.
2016-11-24 18:32:44 -08:00
9f1c668c4f
config: when modifying Parameters, subordinate lookups use top
2016-11-23 20:44:45 -08:00
dae6772624
factor out common cache subcomponents into uncore.util
2016-11-23 12:09:35 -08:00
13190a5de0
rocketchip: re-add AXI4 interface
2016-11-22 17:27:58 -08:00
c230580157
coreplex: rename RocketPlex => RocketTiles
2016-11-22 17:27:58 -08:00
bbabcf67ff
coreplex: width adapter should happen as part of coherence manager
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In the future we will want the L2 to be wider on the backside so that
we can take advantage of fat DDR controllers (256bits/beat).
2016-11-22 17:27:58 -08:00
3d644b943c
coreplex: configString is a property of the RISCVPlatform
2016-11-21 21:13:26 -08:00
e8be365b5d
rocketchip: remove GlobalAddrMap completely
2016-11-21 21:13:26 -08:00
d1328a6b6f
rocketchip: remove most uses of GlobalAddrMap
2016-11-18 19:38:02 -08:00
001d9821bd
Merge remote-tracking branch 'origin/master' into tl2-tile
2016-11-18 18:19:41 -08:00
be8121eeaf
coreplex: fix clock crossing
2016-11-18 17:15:57 -08:00
0082d713af
coreplex: disable Stateless config until we implement adapter
2016-11-18 16:23:16 -08:00
a6188efc41
rocketchip: break infinite Config loops
2016-11-18 16:18:33 -08:00
37a3c22639
rocketchip: move from using cde to config
2016-11-18 16:18:33 -08:00
30425d1665
rocketchip: eliminate all Knobs
2016-11-18 14:31:42 -08:00
bab504cc3f
Add various granular and composable configs.
2016-11-18 11:30:07 -08:00
179c93db42
tilelink2 broadcast: make it controlled via Config
2016-11-17 17:26:49 -08:00
c82b371354
rocketchip: remove obsolete TL1 config
2016-11-17 14:24:45 -08:00
dfc3a0dafb
tilelink2: do not depend on obsolete TL1 configuration
2016-11-17 14:07:53 -08:00
24e3216fcf
coreplex: allow zero interrupt sink/sources
2016-11-16 16:50:36 -08:00
06a7b95d0d
tilelink2 broadcast: support bufferless Config
2016-11-16 12:25:11 -08:00
10e459fedb
rocket: change connection between rocketchip and coreplex
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* rtc and dtm are now crossed half-and-half on the two sides
* groundtest no longer uses riscv platform traits
2016-11-15 18:27:52 -08:00
71315d5cf5
WIP scala compile and firrtl elaborate; monitor error
2016-11-11 13:07:45 -08:00
32fd11935c
rocketchip: use TL2 and AXI4 for memory subsytem
2016-11-04 13:36:47 -07:00
4a2cf6431b
coreplex: make 'mem' port an Option until we can use a Seq
2016-11-04 13:35:36 -07:00
8f757a9135
coreplex: rename BankedL2 trait to BankedL2CoherenceManagers
2016-11-04 13:35:36 -07:00
d03046d11c
coreplex: fix BankedL2 line width
2016-11-04 13:35:36 -07:00
da3cc3b299
coreplex: TileLink2 l1tol2 memory channels
2016-11-03 22:18:28 -07:00
f83d1d0aaf
coreplex: rename trait CoreplexRISCVPlatform
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This makes it clear we are talking about the devices one expects in the
platform, not the ISA.
2016-10-31 11:42:47 -07:00
4a0b29850c
coreplex: reattach clint interrupt
2016-10-31 11:42:47 -07:00
aabd17d935
rocketchip: must create bundles within Module scope
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1. Bundles be created after base class Module constructor runs
2. Bundles must be created before Module(...) runs
Solution: pass a bundle constructor to the cake base class
Require the constructor to take a parameter so people don't use it by
accident; they should get a type error.
Consistently name all the cake arguments with an _io, _coreplex, _outer,
so that they don't shadow the base class variables you should be using.
2016-10-31 11:42:47 -07:00
d52615c39e
coreplex: one IntNode per tile
2016-10-31 11:42:47 -07:00
e97844f71e
coreplex: make it possible to override the ConfigString
2016-10-31 11:42:47 -07:00
688e1bffdf
rocketchip: pull rtcTick out of the coreplex
2016-10-31 11:42:47 -07:00
d51b0b5c02
rocketchip: use self-type
2016-10-31 11:42:47 -07:00
841a31479a
coreplex: fix TinyConfig
2016-10-31 11:42:47 -07:00
ba529c3716
rocketchip: use TileLink2 interrupts
2016-10-31 11:42:47 -07:00
6505431eac
coreplex: use self-type constraints
2016-10-31 11:42:47 -07:00
ac886026e6
rocketchip: reduce number of type parameters
2016-10-31 11:42:47 -07:00
401fd378b4
rocketchip: include devices from cbus in ConfigString
2016-10-31 11:42:13 -07:00
a73aa351ca
rocketchip: fix all clock crossings
2016-10-31 11:42:13 -07:00
825c253a72
rocketchip: move TL2 and cake pattern into Coreplex
2016-10-31 11:42:13 -07:00
dddb50a942
BuildTiles: convert to LazyTile
2016-10-31 11:42:13 -07:00
b99662796d
PLIC: converted to TL2
2016-10-31 11:42:13 -07:00
bddfa4d69b
Debug: make address configurable
2016-10-31 11:42:13 -07:00