From d8ffecf5653d4261a00caab33828081e984aa2ba Mon Sep 17 00:00:00 2001
From: Rimas Avizienis <rimas@eecs.berkeley.edu>
Date: Tue, 1 Nov 2011 22:10:06 -0700
Subject: [PATCH] dcache fix

---
 rocket/src/main/scala/ctrl.scala  | 6 ++++--
 rocket/src/main/scala/dpath.scala | 2 +-
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala
index cf3fff30..ed70dc74 100644
--- a/rocket/src/main/scala/ctrl.scala
+++ b/rocket/src/main/scala/ctrl.scala
@@ -305,6 +305,7 @@ class rocketCtrl extends Component
   val mem_cmd_load = mem_reg_mem_val && (mem_reg_mem_cmd === M_XRD);
   val replay_mem_pc_plus4 = mem_cmd_load && !io.dmem.resp_val;
   val dcache_miss = Reg(replay_mem_pc_plus4);
+  val replay_mem = replay_mem_pc | replay_mem_pc_plus4;
   
   io.dpath.mem_load := mem_cmd_load;
   io.dpath.dcache_miss := dcache_miss;
@@ -318,7 +319,7 @@ class rocketCtrl extends Component
     Mux(jr_taken,                    PC_JR,
     Mux(j_taken,                     PC_J,
     Mux(io.dpath.btb_hit,            PC_BTB,
-        PC_4)))))));
+        PC_4))))))));
 
   io.dpath.wen_btb := ~ex_reg_btb_hit & br_taken;
 
@@ -330,7 +331,8 @@ class rocketCtrl extends Component
     io.dpath.exception |
     ex_reg_privileged |
     ex_reg_eret |
-    replay_mem;
+    replay_mem_pc |
+    replay_mem_pc_plus4;
 
   io.dpath.stallf :=
     ~take_pc &
diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala
index 1f6a287e..af4240e6 100644
--- a/rocket/src/main/scala/dpath.scala
+++ b/rocket/src/main/scala/dpath.scala
@@ -132,7 +132,7 @@ class rocketDpath extends Component
     Mux(io.ctrl.sel_pc === PC_PCR, ex_pcr(31,0).toUFix,
     Mux(io.ctrl.sel_pc === PC_MEM, mem_reg_pc, 
     Mux(io.ctrl.sel_pc === PC_MEM4, mem_reg_pc_plus4, 
-        UFix(0, 32)))))))));
+        UFix(0, 32))))))))));
 
   when (!io.host.start){
     if_reg_pc <== UFix(0, 32); //32'hFFFF_FFFC;