diff --git a/src/main/scala/devices/debug/Debug.scala b/src/main/scala/devices/debug/Debug.scala index 618f155d..112ca367 100644 --- a/src/main/scala/devices/debug/Debug.scala +++ b/src/main/scala/devices/debug/Debug.scala @@ -1029,12 +1029,12 @@ class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int)(implici val innerCtrl = new AsyncBundle(1, new DebugInternalBundle()).flip // This comes from tlClk domain. val debugUnavail = Vec(getNComponents(), Bool()).asInput + val psd = new PSDTestMode().asInput } dmInner.module.io.innerCtrl := FromAsyncBundle(io.innerCtrl) - dmInner.module.io.dmactive := ~ResetCatchAndSync(clock, ~io.dmactive) + dmInner.module.io.dmactive := ~ResetCatchAndSync(clock, ~io.dmactive, "dmactiveSync", io.psd) dmInner.module.io.debugUnavail := io.debugUnavail - } } @@ -1067,6 +1067,7 @@ class TLDebugModule(implicit p: Parameters) extends LazyModule { val dmi = new ClockedDMIIO().flip val in = node.bundleIn val debugInterrupts = intnode.bundleOut + val psd = new PSDTestMode().asInput } dmOuter.module.io.dmi <> io.dmi.dmi @@ -1077,6 +1078,8 @@ class TLDebugModule(implicit p: Parameters) extends LazyModule { dmInner.module.io.dmactive := dmOuter.module.io.ctrl.dmactive dmInner.module.io.debugUnavail := io.ctrl.debugUnavail + dmInner.module.io.psd <> io.psd + io.ctrl <> dmOuter.module.io.ctrl } diff --git a/src/main/scala/devices/debug/Periphery.scala b/src/main/scala/devices/debug/Periphery.scala index 9ab84e8b..3d563daa 100644 --- a/src/main/scala/devices/debug/Periphery.scala +++ b/src/main/scala/devices/debug/Periphery.scala @@ -3,7 +3,7 @@ package freechips.rocketchip.devices.debug import Chisel._ -import chisel3.core.{IntParam} +import chisel3.core.{IntParam, Input, Output} import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.coreplex.HasPeripheryBus import freechips.rocketchip.devices.tilelink._ @@ -15,7 +15,8 @@ import freechips.rocketchip.util._ case object IncludeJtagDTM extends Field[Boolean](false) /** A wrapper bundle containing one of the two possible debug interfaces */ -class DebugIO(implicit p: Parameters) extends ParameterizedBundle()(p) { + +class DebugIO(implicit val p: Parameters) extends ParameterizedBundle()(p) with CanHavePSDTestModeIO { val clockeddmi = (!p(IncludeJtagDTM)).option(new ClockedDMIIO().flip) val systemjtag = (p(IncludeJtagDTM)).option(new SystemJTAGIO) val ndreset = Bool(OUTPUT) @@ -38,7 +39,12 @@ trait HasPeripheryDebugBundle { val debug: DebugIO - def connectDebug(c: Clock, r: Bool, out: Bool, tckHalfPeriod: Int = 2, cmdDelay: Int = 2) { + def connectDebug(c: Clock, + r: Bool, + out: Bool, + tckHalfPeriod: Int = 2, + cmdDelay: Int = 2, + psd: PSDTestMode = new PSDTestMode().fromBits(0.U)): Unit = { debug.clockeddmi.foreach { d => val dtm = Module(new SimDTM).connect(c, r, d, out) } @@ -46,9 +52,10 @@ trait HasPeripheryDebugBundle { val jtag = Module(new JTAGVPI(tckHalfPeriod = tckHalfPeriod, cmdDelay = cmdDelay)).connect(sj.jtag, sj.reset, r, out) sj.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W) } + debug.psd.foreach { _ <> psd } } -} +} trait HasPeripheryDebugModuleImp extends LazyMultiIOModuleImp with HasPeripheryDebugBundle { val outer: HasPeripheryDebug @@ -57,6 +64,7 @@ trait HasPeripheryDebugModuleImp extends LazyMultiIOModuleImp with HasPeripheryD debug.clockeddmi.foreach { dbg => outer.debug.module.io.dmi <> dbg } val dtm = debug.systemjtag.map { sj => + val dtm = Module(new DebugTransportModuleJTAG(p(DebugModuleParams).nDMIAddrSize, p(JtagDTMKey))) dtm.io.jtag <> sj.jtag @@ -67,7 +75,10 @@ trait HasPeripheryDebugModuleImp extends LazyMultiIOModuleImp with HasPeripheryD outer.debug.module.io.dmi.dmi <> dtm.io.dmi outer.debug.module.io.dmi.dmiClock := sj.jtag.TCK - outer.debug.module.io.dmi.dmiReset := ResetCatchAndSync(sj.jtag.TCK, sj.reset, "dmiResetCatch") + + val psd = debug.psd.getOrElse(Wire(new PSDTestMode).fromBits(0.U)) + outer.debug.module.io.psd <> psd + outer.debug.module.io.dmi.dmiReset := ResetCatchAndSync(sj.jtag.TCK, sj.reset, "dmiResetCatch", psd) dtm } diff --git a/src/main/scala/util/PSDTestMode.scala b/src/main/scala/util/PSDTestMode.scala new file mode 100644 index 00000000..c4898bf4 --- /dev/null +++ b/src/main/scala/util/PSDTestMode.scala @@ -0,0 +1,19 @@ +// See LICENSE.SiFive for license details. + +package freechips.rocketchip.util + +import Chisel._ +import freechips.rocketchip.config._ + +case object IncludePSDTest extends Field[Boolean](false) + +class PSDTestMode extends Bundle { + val test_mode = Bool() + val test_mode_reset = Bool() + // TODO: Clocks? +} + +trait CanHavePSDTestModeIO { + implicit val p: Parameters + val psd = p(IncludePSDTest).option(new PSDTestMode().asInput) +} diff --git a/src/main/scala/util/ResetCatchAndSync.scala b/src/main/scala/util/ResetCatchAndSync.scala index 776d94d4..343ca939 100644 --- a/src/main/scala/util/ResetCatchAndSync.scala +++ b/src/main/scala/util/ResetCatchAndSync.scala @@ -11,27 +11,37 @@ import Chisel._ class ResetCatchAndSync (sync: Int = 3) extends Module { + override def desiredName = s"ResetCatchAndSync_d${sync}" + val io = new Bundle { val sync_reset = Bool(OUTPUT) + val psd = new PSDTestMode().asInput } - io.sync_reset := ~AsyncResetSynchronizerShiftReg(Bool(true), sync) + io.sync_reset := Mux(io.psd.test_mode, io.psd.test_mode_reset, + ~AsyncResetSynchronizerShiftReg(Bool(true), sync)) } object ResetCatchAndSync { - def apply(clk: Clock, rst: Bool, sync: Int = 3, name: Option[String] = None): Bool = { + def apply(clk: Clock, rst: Bool, sync: Int = 3, name: Option[String] = None, + psd: Option[PSDTestMode] = None): Bool = { val catcher = Module (new ResetCatchAndSync(sync)) if (name.isDefined) {catcher.suggestName(name.get)} catcher.clock := clk catcher.reset := rst - + catcher.io.psd <> psd.getOrElse(Wire(new PSDTestMode()).fromBits(UInt(0))) catcher.io.sync_reset } def apply(clk: Clock, rst: Bool, sync: Int, name: String): Bool = apply(clk, rst, sync, Some(name)) def apply(clk: Clock, rst: Bool, name: String): Bool = apply(clk, rst, name = Some(name)) + def apply(clk: Clock, rst: Bool, sync: Int, name: String, psd: PSDTestMode): Bool = + apply(clk, rst, sync, Some(name), Some(psd)) + def apply(clk: Clock, rst: Bool, name: String, psd: PSDTestMode): Bool = + apply(clk, rst, name = Some(name), psd = Some(psd)) + }