From 82c00cb656833dceff3dd7927117b332d0d3755e Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Tue, 12 Sep 2017 16:05:13 -0700 Subject: [PATCH 1/7] reset_catch: Allow Test Mode Overrides --- src/main/scala/devices/debug/Debug.scala | 7 +++++-- src/main/scala/devices/debug/Periphery.scala | 16 ++++++++++------ src/main/scala/util/ResetCatchAndSync.scala | 17 +++++++++++++++-- 3 files changed, 30 insertions(+), 10 deletions(-) diff --git a/src/main/scala/devices/debug/Debug.scala b/src/main/scala/devices/debug/Debug.scala index 618f155d..a541cbe4 100644 --- a/src/main/scala/devices/debug/Debug.scala +++ b/src/main/scala/devices/debug/Debug.scala @@ -1029,12 +1029,12 @@ class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int)(implici val innerCtrl = new AsyncBundle(1, new DebugInternalBundle()).flip // This comes from tlClk domain. val debugUnavail = Vec(getNComponents(), Bool()).asInput + val psd = new PSDTestModeIO() } dmInner.module.io.innerCtrl := FromAsyncBundle(io.innerCtrl) - dmInner.module.io.dmactive := ~ResetCatchAndSync(clock, ~io.dmactive) + dmInner.module.io.dmactive := ~ResetCatchAndSync(clock, ~io.dmactive, 3, Some("dmactiveSync"), io.psd.test_mode, io.psd.test_mode_reset) dmInner.module.io.debugUnavail := io.debugUnavail - } } @@ -1067,6 +1067,7 @@ class TLDebugModule(implicit p: Parameters) extends LazyModule { val dmi = new ClockedDMIIO().flip val in = node.bundleIn val debugInterrupts = intnode.bundleOut + val psd = new PSDTestModeIO() } dmOuter.module.io.dmi <> io.dmi.dmi @@ -1077,6 +1078,8 @@ class TLDebugModule(implicit p: Parameters) extends LazyModule { dmInner.module.io.dmactive := dmOuter.module.io.ctrl.dmactive dmInner.module.io.debugUnavail := io.ctrl.debugUnavail + io.psd <> dmInner.module.io.psd + io.ctrl <> dmOuter.module.io.ctrl } diff --git a/src/main/scala/devices/debug/Periphery.scala b/src/main/scala/devices/debug/Periphery.scala index 776c0632..5770dedd 100644 --- a/src/main/scala/devices/debug/Periphery.scala +++ b/src/main/scala/devices/debug/Periphery.scala @@ -3,7 +3,7 @@ package freechips.rocketchip.devices.debug import Chisel._ -import chisel3.core.{IntParam} +import chisel3.core.{IntParam, Input, Output} import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.coreplex.HasPeripheryBus import freechips.rocketchip.devices.tilelink._ @@ -12,10 +12,10 @@ import freechips.rocketchip.jtag._ import freechips.rocketchip.util._ /** A knob selecting one of the two possible debug interfaces */ -case object IncludeJtagDTM extends Field[Boolean] - +case object IncludeJtagDTM extends Field[Boolean](false) /** A wrapper bundle containing one of the two possible debug interfaces */ -class DebugIO(implicit p: Parameters) extends ParameterizedBundle()(p) { + +class DebugIO(implicit val p: Parameters) extends ParameterizedBundle()(p) with CanHavePSDTestModeIO { val clockeddmi = (!p(IncludeJtagDTM)).option(new ClockedDMIIO().flip) val systemjtag = (p(IncludeJtagDTM)).option(new SystemJTAGIO) val ndreset = Bool(OUTPUT) @@ -48,7 +48,6 @@ trait HasPeripheryDebugBundle { } } } - trait HasPeripheryDebugModuleImp extends LazyMultiIOModuleImp with HasPeripheryDebugBundle { val outer: HasPeripheryDebug @@ -57,6 +56,9 @@ trait HasPeripheryDebugModuleImp extends LazyMultiIOModuleImp with HasPeripheryD debug.clockeddmi.foreach { dbg => outer.debug.module.io.dmi <> dbg } val dtm = debug.systemjtag.map { sj => + + val psd = debug.psd.getOrElse(Wire(init = new PSDTestModeIO().fromBits(0.U))) + val dtm = Module(new DebugTransportModuleJTAG(p(DebugModuleParams).nDMIAddrSize, p(JtagDTMKey))) dtm.io.jtag <> sj.jtag @@ -67,7 +69,9 @@ trait HasPeripheryDebugModuleImp extends LazyMultiIOModuleImp with HasPeripheryD outer.debug.module.io.dmi.dmi <> dtm.io.dmi outer.debug.module.io.dmi.dmiClock := sj.jtag.TCK - outer.debug.module.io.dmi.dmiReset := ResetCatchAndSync(sj.jtag.TCK, sj.reset, "dmiResetCatch") + + outer.debug.module.io.psd <> psd + outer.debug.module.io.dmi.dmiReset := ResetCatchAndSync(sj.jtag.TCK, sj.reset, "dmiResetCatch", psd.test_mode, psd.test_mode_reset) dtm } diff --git a/src/main/scala/util/ResetCatchAndSync.scala b/src/main/scala/util/ResetCatchAndSync.scala index 776d94d4..ab2f52f9 100644 --- a/src/main/scala/util/ResetCatchAndSync.scala +++ b/src/main/scala/util/ResetCatchAndSync.scala @@ -11,22 +11,30 @@ import Chisel._ class ResetCatchAndSync (sync: Int = 3) extends Module { + override def desiredName = s"ResetCatchAndSync_d${sync}" + val io = new Bundle { val sync_reset = Bool(OUTPUT) + val psd_test_reset = Bool(INPUT) + val psd_test_mode = Bool(INPUT) } - io.sync_reset := ~AsyncResetSynchronizerShiftReg(Bool(true), sync) + io.sync_reset := Mux(io.psd_test_mode, io.psd_test_reset, + ~AsyncResetSynchronizerShiftReg(Bool(true), sync)) } object ResetCatchAndSync { - def apply(clk: Clock, rst: Bool, sync: Int = 3, name: Option[String] = None): Bool = { + def apply(clk: Clock, rst: Bool, sync: Int = 3, name: Option[String] = None, + psd_test_mode: Bool = Bool(false), psd_test_reset: Bool = Bool(false)): Bool = { val catcher = Module (new ResetCatchAndSync(sync)) if (name.isDefined) {catcher.suggestName(name.get)} catcher.clock := clk catcher.reset := rst + catcher.io.psd_test_mode := psd_test_mode + catcher.io.psd_test_reset:= psd_test_reset catcher.io.sync_reset } @@ -34,4 +42,9 @@ object ResetCatchAndSync { def apply(clk: Clock, rst: Bool, sync: Int, name: String): Bool = apply(clk, rst, sync, Some(name)) def apply(clk: Clock, rst: Bool, name: String): Bool = apply(clk, rst, name = Some(name)) + def apply(clk: Clock, rst: Bool, sync: Int, name: String, psd_test_mode: Bool, psd_test_reset: Bool): Bool = apply(clk, rst, sync, Some(name), + psd_test_mode, psd_test_reset) + def apply(clk: Clock, rst: Bool, name: String, psd_test_mode: Bool, psd_test_reset: Bool): Bool = apply(clk, rst, name = Some(name), + psd_test_mode = psd_test_mode, psd_test_reset = psd_test_reset) + } From 44edc5fdc38d2de648c739db66f782d95bfabcef Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Wed, 13 Sep 2017 17:00:01 -0700 Subject: [PATCH 2/7] test_mode_reset: Use simpler apply() method --- src/main/scala/devices/debug/Debug.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/devices/debug/Debug.scala b/src/main/scala/devices/debug/Debug.scala index a541cbe4..8b0b9c70 100644 --- a/src/main/scala/devices/debug/Debug.scala +++ b/src/main/scala/devices/debug/Debug.scala @@ -1033,7 +1033,7 @@ class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int)(implici } dmInner.module.io.innerCtrl := FromAsyncBundle(io.innerCtrl) - dmInner.module.io.dmactive := ~ResetCatchAndSync(clock, ~io.dmactive, 3, Some("dmactiveSync"), io.psd.test_mode, io.psd.test_mode_reset) + dmInner.module.io.dmactive := ~ResetCatchAndSync(clock, ~io.dmactive, "dmactiveSync", io.psd.test_mode, io.psd.test_mode_reset) dmInner.module.io.debugUnavail := io.debugUnavail } } From a0396b63e8d8e54c4434b767b206d792b6db02cd Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Thu, 14 Sep 2017 13:15:24 -0700 Subject: [PATCH 3/7] test_mode_reset: fix one bulk-connect gender issue --- src/main/scala/devices/debug/Periphery.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/devices/debug/Periphery.scala b/src/main/scala/devices/debug/Periphery.scala index 5770dedd..3fd4ecf9 100644 --- a/src/main/scala/devices/debug/Periphery.scala +++ b/src/main/scala/devices/debug/Periphery.scala @@ -70,7 +70,7 @@ trait HasPeripheryDebugModuleImp extends LazyMultiIOModuleImp with HasPeripheryD outer.debug.module.io.dmi.dmi <> dtm.io.dmi outer.debug.module.io.dmi.dmiClock := sj.jtag.TCK - outer.debug.module.io.psd <> psd + psd <> outer.debug.module.io.psd outer.debug.module.io.dmi.dmiReset := ResetCatchAndSync(sj.jtag.TCK, sj.reset, "dmiResetCatch", psd.test_mode, psd.test_mode_reset) dtm } From ffc514d1bca1d562a27fc987db933f300ba13a49 Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Thu, 14 Sep 2017 13:17:37 -0700 Subject: [PATCH 4/7] test_mode_reset: Add missing file --- src/main/scala/util/PSDTestMode.scala | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 src/main/scala/util/PSDTestMode.scala diff --git a/src/main/scala/util/PSDTestMode.scala b/src/main/scala/util/PSDTestMode.scala new file mode 100644 index 00000000..ae4a3942 --- /dev/null +++ b/src/main/scala/util/PSDTestMode.scala @@ -0,0 +1,19 @@ +// See LICENSE.SiFive for license details. + +package freechips.rocketchip.util + +import Chisel._ +import freechips.rocketchip.config._ + +case object IncludePSDTest extends Field[Boolean](false) + +class PSDTestModeIO extends Bundle { + val test_mode = Bool(INPUT) + val test_mode_reset = Bool(INPUT) + // TODO: Clocks? +} + +trait CanHavePSDTestModeIO { + implicit val p: Parameters + val psd = p(IncludePSDTest).option(new PSDTestModeIO()) +} From 6cda4504acd023ab77d8b88f1b03e8a6e0ec0876 Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Fri, 15 Sep 2017 12:30:39 -0700 Subject: [PATCH 5/7] test_mode_reset: use a cleaner interface with bundles and options instead of individual signals --- src/main/scala/devices/debug/Debug.scala | 6 +++--- src/main/scala/devices/debug/Periphery.scala | 4 ++-- src/main/scala/util/PSDTestMode.scala | 8 ++++---- src/main/scala/util/ResetCatchAndSync.scala | 21 +++++++++----------- 4 files changed, 18 insertions(+), 21 deletions(-) diff --git a/src/main/scala/devices/debug/Debug.scala b/src/main/scala/devices/debug/Debug.scala index 8b0b9c70..fee423e7 100644 --- a/src/main/scala/devices/debug/Debug.scala +++ b/src/main/scala/devices/debug/Debug.scala @@ -1029,11 +1029,11 @@ class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int)(implici val innerCtrl = new AsyncBundle(1, new DebugInternalBundle()).flip // This comes from tlClk domain. val debugUnavail = Vec(getNComponents(), Bool()).asInput - val psd = new PSDTestModeIO() + val psd = new PSDTestMode().asInput } dmInner.module.io.innerCtrl := FromAsyncBundle(io.innerCtrl) - dmInner.module.io.dmactive := ~ResetCatchAndSync(clock, ~io.dmactive, "dmactiveSync", io.psd.test_mode, io.psd.test_mode_reset) + dmInner.module.io.dmactive := ~ResetCatchAndSync(clock, ~io.dmactive, "dmactiveSync", io.psd) dmInner.module.io.debugUnavail := io.debugUnavail } } @@ -1067,7 +1067,7 @@ class TLDebugModule(implicit p: Parameters) extends LazyModule { val dmi = new ClockedDMIIO().flip val in = node.bundleIn val debugInterrupts = intnode.bundleOut - val psd = new PSDTestModeIO() + val psd = new PSDTestMode() } dmOuter.module.io.dmi <> io.dmi.dmi diff --git a/src/main/scala/devices/debug/Periphery.scala b/src/main/scala/devices/debug/Periphery.scala index 3fd4ecf9..9a096c8f 100644 --- a/src/main/scala/devices/debug/Periphery.scala +++ b/src/main/scala/devices/debug/Periphery.scala @@ -57,7 +57,7 @@ trait HasPeripheryDebugModuleImp extends LazyMultiIOModuleImp with HasPeripheryD val dtm = debug.systemjtag.map { sj => - val psd = debug.psd.getOrElse(Wire(init = new PSDTestModeIO().fromBits(0.U))) + val psd = debug.psd.getOrElse(Wire(init = new PSDTestMode().fromBits(0.U))) val dtm = Module(new DebugTransportModuleJTAG(p(DebugModuleParams).nDMIAddrSize, p(JtagDTMKey))) dtm.io.jtag <> sj.jtag @@ -71,7 +71,7 @@ trait HasPeripheryDebugModuleImp extends LazyMultiIOModuleImp with HasPeripheryD outer.debug.module.io.dmi.dmiClock := sj.jtag.TCK psd <> outer.debug.module.io.psd - outer.debug.module.io.dmi.dmiReset := ResetCatchAndSync(sj.jtag.TCK, sj.reset, "dmiResetCatch", psd.test_mode, psd.test_mode_reset) + outer.debug.module.io.dmi.dmiReset := ResetCatchAndSync(sj.jtag.TCK, sj.reset, "dmiResetCatch", psd) dtm } diff --git a/src/main/scala/util/PSDTestMode.scala b/src/main/scala/util/PSDTestMode.scala index ae4a3942..c4898bf4 100644 --- a/src/main/scala/util/PSDTestMode.scala +++ b/src/main/scala/util/PSDTestMode.scala @@ -7,13 +7,13 @@ import freechips.rocketchip.config._ case object IncludePSDTest extends Field[Boolean](false) -class PSDTestModeIO extends Bundle { - val test_mode = Bool(INPUT) - val test_mode_reset = Bool(INPUT) +class PSDTestMode extends Bundle { + val test_mode = Bool() + val test_mode_reset = Bool() // TODO: Clocks? } trait CanHavePSDTestModeIO { implicit val p: Parameters - val psd = p(IncludePSDTest).option(new PSDTestModeIO()) + val psd = p(IncludePSDTest).option(new PSDTestMode().asInput) } diff --git a/src/main/scala/util/ResetCatchAndSync.scala b/src/main/scala/util/ResetCatchAndSync.scala index ab2f52f9..dc050a6b 100644 --- a/src/main/scala/util/ResetCatchAndSync.scala +++ b/src/main/scala/util/ResetCatchAndSync.scala @@ -15,11 +15,10 @@ class ResetCatchAndSync (sync: Int = 3) extends Module { val io = new Bundle { val sync_reset = Bool(OUTPUT) - val psd_test_reset = Bool(INPUT) - val psd_test_mode = Bool(INPUT) + val psd = new PSDTestMode().asInput } - io.sync_reset := Mux(io.psd_test_mode, io.psd_test_reset, + io.sync_reset := Mux(io.psd.test_mode, io.psd.test_mode_reset, ~AsyncResetSynchronizerShiftReg(Bool(true), sync)) } @@ -27,24 +26,22 @@ class ResetCatchAndSync (sync: Int = 3) extends Module { object ResetCatchAndSync { def apply(clk: Clock, rst: Bool, sync: Int = 3, name: Option[String] = None, - psd_test_mode: Bool = Bool(false), psd_test_reset: Bool = Bool(false)): Bool = { + psd: Option[PSDTestMode] =None): Bool = { val catcher = Module (new ResetCatchAndSync(sync)) if (name.isDefined) {catcher.suggestName(name.get)} catcher.clock := clk catcher.reset := rst - catcher.io.psd_test_mode := psd_test_mode - catcher.io.psd_test_reset:= psd_test_reset - + catcher.io.psd <> psd.getOrElse(Wire(new PSDTestMode()).fromBits(UInt(0))) catcher.io.sync_reset } def apply(clk: Clock, rst: Bool, sync: Int, name: String): Bool = apply(clk, rst, sync, Some(name)) def apply(clk: Clock, rst: Bool, name: String): Bool = apply(clk, rst, name = Some(name)) - def apply(clk: Clock, rst: Bool, sync: Int, name: String, psd_test_mode: Bool, psd_test_reset: Bool): Bool = apply(clk, rst, sync, Some(name), - psd_test_mode, psd_test_reset) - def apply(clk: Clock, rst: Bool, name: String, psd_test_mode: Bool, psd_test_reset: Bool): Bool = apply(clk, rst, name = Some(name), - psd_test_mode = psd_test_mode, psd_test_reset = psd_test_reset) - + def apply(clk: Clock, rst: Bool, sync: Int, name: String, psd: PSDTestMode): Bool = + apply(clk, rst, sync, Some(name), Some(psd)) + def apply(clk: Clock, rst: Bool, name: String, psd: PSDTestMode): Bool = + apply(clk, rst, name = Some(name), psd = Some(psd)) + } From 641a8e7eabdb765c51dad92228d7d55c2cbf3eaa Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Fri, 15 Sep 2017 16:36:35 -0700 Subject: [PATCH 6/7] test_mode_reset: Correct some gender issues. Tie off signals in the test harness --- src/main/scala/devices/debug/Debug.scala | 4 ++-- src/main/scala/devices/debug/Periphery.scala | 14 +++++++++----- src/main/scala/util/ResetCatchAndSync.scala | 2 +- 3 files changed, 12 insertions(+), 8 deletions(-) diff --git a/src/main/scala/devices/debug/Debug.scala b/src/main/scala/devices/debug/Debug.scala index fee423e7..112ca367 100644 --- a/src/main/scala/devices/debug/Debug.scala +++ b/src/main/scala/devices/debug/Debug.scala @@ -1067,7 +1067,7 @@ class TLDebugModule(implicit p: Parameters) extends LazyModule { val dmi = new ClockedDMIIO().flip val in = node.bundleIn val debugInterrupts = intnode.bundleOut - val psd = new PSDTestMode() + val psd = new PSDTestMode().asInput } dmOuter.module.io.dmi <> io.dmi.dmi @@ -1078,7 +1078,7 @@ class TLDebugModule(implicit p: Parameters) extends LazyModule { dmInner.module.io.dmactive := dmOuter.module.io.ctrl.dmactive dmInner.module.io.debugUnavail := io.ctrl.debugUnavail - io.psd <> dmInner.module.io.psd + dmInner.module.io.psd <> io.psd io.ctrl <> dmOuter.module.io.ctrl diff --git a/src/main/scala/devices/debug/Periphery.scala b/src/main/scala/devices/debug/Periphery.scala index 9a096c8f..d1e05653 100644 --- a/src/main/scala/devices/debug/Periphery.scala +++ b/src/main/scala/devices/debug/Periphery.scala @@ -38,7 +38,7 @@ trait HasPeripheryDebugBundle { val debug: DebugIO - def connectDebug(c: Clock, r: Bool, out: Bool, tckHalfPeriod: Int = 2, cmdDelay: Int = 2) { + def connectDebug(c: Clock, r: Bool, out: Bool, tckHalfPeriod: Int = 2, cmdDelay: Int = 2, psd: PSDTestMode) { debug.clockeddmi.foreach { d => val dtm = Module(new SimDTM).connect(c, r, d, out) } @@ -46,7 +46,12 @@ trait HasPeripheryDebugBundle { val jtag = Module(new JTAGVPI(tckHalfPeriod = tckHalfPeriod, cmdDelay = cmdDelay)).connect(sj.jtag, sj.reset, r, out) sj.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W) } + debug.psd.foreach { _ <> psd } } + + def connectDebug(c: Clock, r: Bool, out: Bool, tckHalfPeriod: Int = 2, cmdDelay: Int = 2) = + connectDebug(c, r, out, tckHalfPeriod, cmdDelay, new PSDTestMode.fromBits(0.U)) + } trait HasPeripheryDebugModuleImp extends LazyMultiIOModuleImp with HasPeripheryDebugBundle { val outer: HasPeripheryDebug @@ -57,8 +62,6 @@ trait HasPeripheryDebugModuleImp extends LazyMultiIOModuleImp with HasPeripheryD val dtm = debug.systemjtag.map { sj => - val psd = debug.psd.getOrElse(Wire(init = new PSDTestMode().fromBits(0.U))) - val dtm = Module(new DebugTransportModuleJTAG(p(DebugModuleParams).nDMIAddrSize, p(JtagDTMKey))) dtm.io.jtag <> sj.jtag @@ -70,8 +73,9 @@ trait HasPeripheryDebugModuleImp extends LazyMultiIOModuleImp with HasPeripheryD outer.debug.module.io.dmi.dmi <> dtm.io.dmi outer.debug.module.io.dmi.dmiClock := sj.jtag.TCK - psd <> outer.debug.module.io.psd - outer.debug.module.io.dmi.dmiReset := ResetCatchAndSync(sj.jtag.TCK, sj.reset, "dmiResetCatch", psd) + val psd = debug.psd.getOrElse(Wire(new PSDTestMode).fromBits(0.U)) + outer.debug.module.io.psd <> psd + outer.debug.module.io.dmi.dmiReset := ResetCatchAndSync(sj.jtag.TCK, sj.reset, "dmiResetCatch", psd) dtm } diff --git a/src/main/scala/util/ResetCatchAndSync.scala b/src/main/scala/util/ResetCatchAndSync.scala index dc050a6b..343ca939 100644 --- a/src/main/scala/util/ResetCatchAndSync.scala +++ b/src/main/scala/util/ResetCatchAndSync.scala @@ -26,7 +26,7 @@ class ResetCatchAndSync (sync: Int = 3) extends Module { object ResetCatchAndSync { def apply(clk: Clock, rst: Bool, sync: Int = 3, name: Option[String] = None, - psd: Option[PSDTestMode] =None): Bool = { + psd: Option[PSDTestMode] = None): Bool = { val catcher = Module (new ResetCatchAndSync(sync)) if (name.isDefined) {catcher.suggestName(name.get)} From 215e072e5c4ffd5ec5582464555336e13943cb6c Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Sun, 17 Sep 2017 13:51:40 -0700 Subject: [PATCH 7/7] test_mode_reset: fix typos --- src/main/scala/devices/debug/Periphery.scala | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/src/main/scala/devices/debug/Periphery.scala b/src/main/scala/devices/debug/Periphery.scala index d1e05653..ecd612d9 100644 --- a/src/main/scala/devices/debug/Periphery.scala +++ b/src/main/scala/devices/debug/Periphery.scala @@ -38,7 +38,12 @@ trait HasPeripheryDebugBundle { val debug: DebugIO - def connectDebug(c: Clock, r: Bool, out: Bool, tckHalfPeriod: Int = 2, cmdDelay: Int = 2, psd: PSDTestMode) { + def connectDebug(c: Clock, + r: Bool, + out: Bool, + tckHalfPeriod: Int = 2, + cmdDelay: Int = 2, + psd: PSDTestMode = new PSDTestMode().fromBits(0.U)): Unit = { debug.clockeddmi.foreach { d => val dtm = Module(new SimDTM).connect(c, r, d, out) } @@ -49,9 +54,6 @@ trait HasPeripheryDebugBundle { debug.psd.foreach { _ <> psd } } - def connectDebug(c: Clock, r: Bool, out: Bool, tckHalfPeriod: Int = 2, cmdDelay: Int = 2) = - connectDebug(c, r, out, tckHalfPeriod, cmdDelay, new PSDTestMode.fromBits(0.U)) - } trait HasPeripheryDebugModuleImp extends LazyMultiIOModuleImp with HasPeripheryDebugBundle { val outer: HasPeripheryDebug