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Merge pull request #215 from ucb-bar/test-harness-fixes

Test harness fixes
This commit is contained in:
Scott Johnson 2016-08-22 10:33:01 -07:00 committed by GitHub
commit 8d6f080ed0
2 changed files with 19 additions and 13 deletions

View File

@ -39,7 +39,7 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
$(RISCV)/lib/libfesvr.so \ $(RISCV)/lib/libfesvr.so \
-sverilog \ -sverilog \
+incdir+$(generated_dir) \ +incdir+$(generated_dir) \
+define+CLOCK_PERIOD=0.5 $(sim_vsrcs) $(sim_csrcs) \ +define+CLOCK_PERIOD=1.0 $(sim_vsrcs) $(sim_csrcs) \
+define+PRINTF_COND=$(TB).printf_cond \ +define+PRINTF_COND=$(TB).printf_cond \
+define+STOP_COND=!$(TB).reset \ +define+STOP_COND=!$(TB).reset \
+define+RANDOMIZE \ +define+RANDOMIZE \

View File

@ -5,7 +5,7 @@ module TestDriver;
reg clk = 1'b0; reg clk = 1'b0;
reg reset = 1'b1; reg reset = 1'b1;
always #`CLOCK_PERIOD clk = ~clk; always #(`CLOCK_PERIOD/2.0) clk = ~clk;
initial #777.7 reset = 0; initial #777.7 reset = 0;
// Read input arguments and initialize // Read input arguments and initialize
@ -39,12 +39,25 @@ module TestDriver;
`endif `endif
end end
`ifdef TESTBENCH_IN_UVM
// UVM library has its own way to manage end-of-simulation.
// A UVM-based testbench will raise an objection, watch this signal until this goes 1, then drop the objection.
reg finish_request = 1'b0;
`endif
reg [255:0] reason = ""; reg [255:0] reason = "";
reg failure = 1'b0; reg failure = 1'b0;
wire success; wire success;
integer stderr = 32'h80000002; integer stderr = 32'h80000002;
always @(posedge clk) always @(posedge clk)
begin begin
`ifdef GATE_LEVEL
if (verbose)
begin
$fdisplay(stderr, "C: %10d", trace_count);
end
`endif
trace_count = trace_count + 1;
if (!reset) if (!reset)
begin begin
if (max_cycles > 0 && trace_count > max_cycles) if (max_cycles > 0 && trace_count > max_cycles)
@ -65,21 +78,14 @@ module TestDriver;
if (verbose) if (verbose)
$fdisplay(stderr, "Completed after %d simulation cycles", trace_count); $fdisplay(stderr, "Completed after %d simulation cycles", trace_count);
`VCDPLUSCLOSE `VCDPLUSCLOSE
`ifdef TESTBENCH_IN_UVM
finish_request = 1;
`else
$finish; $finish;
end
end
end
always @(posedge clk)
begin
trace_count = trace_count + 1;
`ifdef GATE_LEVEL
if (verbose)
begin
$fdisplay(stderr, "C: %10d", trace_count-1);
end
`endif `endif
end end
end
end
TestHarness testHarness( TestHarness testHarness(
.clk(clk), .clk(clk),