From f945acf712b91f3d2d1d2769930aef4888291290 Mon Sep 17 00:00:00 2001
From: Scott Johnson <scottj@sifive.com>
Date: Fri, 12 Aug 2016 16:58:22 -0700
Subject: [PATCH 1/4] rm race condition on trace_count

---
 vsrc/TestDriver.v | 18 +++++++-----------
 1 file changed, 7 insertions(+), 11 deletions(-)

diff --git a/vsrc/TestDriver.v b/vsrc/TestDriver.v
index f188c96e..02d2cd54 100644
--- a/vsrc/TestDriver.v
+++ b/vsrc/TestDriver.v
@@ -45,6 +45,13 @@ module TestDriver;
   integer stderr = 32'h80000002;
   always @(posedge clk)
   begin
+    trace_count = trace_count + 1;
+`ifdef GATE_LEVEL
+    if (verbose)
+    begin
+      $fdisplay(stderr, "C: %10d", trace_count-1);
+    end
+`endif
     if (!reset)
     begin
       if (max_cycles > 0 && trace_count > max_cycles)
@@ -70,17 +77,6 @@ module TestDriver;
     end
   end
 
-  always @(posedge clk)
-  begin
-    trace_count = trace_count + 1;
-`ifdef GATE_LEVEL
-    if (verbose)
-    begin
-      $fdisplay(stderr, "C: %10d", trace_count-1);
-    end
-`endif
-  end
-
   TestHarness testHarness(
     .clk(clk),
     .reset(reset),

From 4dbcc568dc1ab93fa9f84ed2e2927504379597ab Mon Sep 17 00:00:00 2001
From: Scott Johnson <scottj@sifive.com>
Date: Fri, 12 Aug 2016 17:03:21 -0700
Subject: [PATCH 2/4] reorder code to get rid of messy -1

---
 vsrc/TestDriver.v | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/vsrc/TestDriver.v b/vsrc/TestDriver.v
index 02d2cd54..92d61812 100644
--- a/vsrc/TestDriver.v
+++ b/vsrc/TestDriver.v
@@ -45,13 +45,14 @@ module TestDriver;
   integer stderr = 32'h80000002;
   always @(posedge clk)
   begin
-    trace_count = trace_count + 1;
 `ifdef GATE_LEVEL
     if (verbose)
     begin
-      $fdisplay(stderr, "C: %10d", trace_count-1);
+      $fdisplay(stderr, "C: %10d", trace_count);
     end
 `endif
+
+    trace_count = trace_count + 1;
     if (!reset)
     begin
       if (max_cycles > 0 && trace_count > max_cycles)

From 2d12f6689ca6e8ff7757f8345a2a30e4f5a27d3e Mon Sep 17 00:00:00 2001
From: Scott Johnson <scottj@sifive.com>
Date: Fri, 19 Aug 2016 14:44:48 -0700
Subject: [PATCH 3/4] make CLOCK_PERIOD actually be the clock period, instead
 of half of the clock period

---
 vsim/Makefrag     | 2 +-
 vsrc/TestDriver.v | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/vsim/Makefrag b/vsim/Makefrag
index 2a129ee8..f4bcb7a5 100644
--- a/vsim/Makefrag
+++ b/vsim/Makefrag
@@ -39,7 +39,7 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
 	$(RISCV)/lib/libfesvr.so \
 	-sverilog \
 	+incdir+$(generated_dir) \
-	+define+CLOCK_PERIOD=0.5 $(sim_vsrcs) $(sim_csrcs) \
+	+define+CLOCK_PERIOD=1.0 $(sim_vsrcs) $(sim_csrcs) \
 	+define+PRINTF_COND=$(TB).printf_cond \
 	+define+STOP_COND=!$(TB).reset \
 	+define+RANDOMIZE \
diff --git a/vsrc/TestDriver.v b/vsrc/TestDriver.v
index 92d61812..8ddcb22c 100644
--- a/vsrc/TestDriver.v
+++ b/vsrc/TestDriver.v
@@ -5,7 +5,7 @@ module TestDriver;
   reg clk   = 1'b0;
   reg reset = 1'b1;
 
-  always #`CLOCK_PERIOD clk = ~clk;
+  always #(`CLOCK_PERIOD/2.0) clk = ~clk;
   initial #777.7 reset = 0;
 
   // Read input arguments and initialize

From 96a868d38888fd30c9685df3c731a946d2da6c34 Mon Sep 17 00:00:00 2001
From: Scott Johnson <scottj@sifive.com>
Date: Fri, 19 Aug 2016 17:14:54 -0700
Subject: [PATCH 4/4] enable the TestDriver to be used in a SystemVerilog
 UVM-based testbench, which has its own way to manage end-of-simulation and
 does not like anyone else to call $finish

---
 vsrc/TestDriver.v | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/vsrc/TestDriver.v b/vsrc/TestDriver.v
index 8ddcb22c..4d5bd632 100644
--- a/vsrc/TestDriver.v
+++ b/vsrc/TestDriver.v
@@ -39,6 +39,11 @@ module TestDriver;
 `endif
   end
 
+`ifdef TESTBENCH_IN_UVM
+  // UVM library has its own way to manage end-of-simulation.
+  // A UVM-based testbench will raise an objection, watch this signal until this goes 1, then drop the objection.
+  reg finish_request = 1'b0;
+`endif
   reg [255:0] reason = "";
   reg failure = 1'b0;
   wire success;
@@ -73,7 +78,11 @@ module TestDriver;
         if (verbose)
           $fdisplay(stderr, "Completed after %d simulation cycles", trace_count);
         `VCDPLUSCLOSE
+`ifdef TESTBENCH_IN_UVM
+        finish_request = 1;
+`else
         $finish;
+`endif
       end
     end
   end