diff --git a/vsim/Makefrag b/vsim/Makefrag index 2a129ee8..f4bcb7a5 100644 --- a/vsim/Makefrag +++ b/vsim/Makefrag @@ -39,7 +39,7 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1 $(RISCV)/lib/libfesvr.so \ -sverilog \ +incdir+$(generated_dir) \ - +define+CLOCK_PERIOD=0.5 $(sim_vsrcs) $(sim_csrcs) \ + +define+CLOCK_PERIOD=1.0 $(sim_vsrcs) $(sim_csrcs) \ +define+PRINTF_COND=$(TB).printf_cond \ +define+STOP_COND=!$(TB).reset \ +define+RANDOMIZE \ diff --git a/vsrc/TestDriver.v b/vsrc/TestDriver.v index f188c96e..4d5bd632 100644 --- a/vsrc/TestDriver.v +++ b/vsrc/TestDriver.v @@ -5,7 +5,7 @@ module TestDriver; reg clk = 1'b0; reg reset = 1'b1; - always #`CLOCK_PERIOD clk = ~clk; + always #(`CLOCK_PERIOD/2.0) clk = ~clk; initial #777.7 reset = 0; // Read input arguments and initialize @@ -39,12 +39,25 @@ module TestDriver; `endif end +`ifdef TESTBENCH_IN_UVM + // UVM library has its own way to manage end-of-simulation. + // A UVM-based testbench will raise an objection, watch this signal until this goes 1, then drop the objection. + reg finish_request = 1'b0; +`endif reg [255:0] reason = ""; reg failure = 1'b0; wire success; integer stderr = 32'h80000002; always @(posedge clk) begin +`ifdef GATE_LEVEL + if (verbose) + begin + $fdisplay(stderr, "C: %10d", trace_count); + end +`endif + + trace_count = trace_count + 1; if (!reset) begin if (max_cycles > 0 && trace_count > max_cycles) @@ -65,22 +78,15 @@ module TestDriver; if (verbose) $fdisplay(stderr, "Completed after %d simulation cycles", trace_count); `VCDPLUSCLOSE +`ifdef TESTBENCH_IN_UVM + finish_request = 1; +`else $finish; +`endif end end end - always @(posedge clk) - begin - trace_count = trace_count + 1; -`ifdef GATE_LEVEL - if (verbose) - begin - $fdisplay(stderr, "C: %10d", trace_count-1); - end -`endif - end - TestHarness testHarness( .clk(clk), .reset(reset),