From 742c05d6a7890af4968ffc2e1bb49cd4f20a50a8 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 13 May 2016 17:07:28 -0700 Subject: [PATCH] Pipeline D$->I$ control paths These stretch the miss latency by a cycle in exchange for slack. The current implementation also adds a cycle to mul/div latency, which can be worked around for more hardware (possibly gated by the FastMulDiv option). --- rocket/src/main/scala/rocket.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/rocket/src/main/scala/rocket.scala b/rocket/src/main/scala/rocket.scala index 03fc0f20..757e870d 100644 --- a/rocket/src/main/scala/rocket.scala +++ b/rocket/src/main/scala/rocket.scala @@ -450,7 +450,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) { val sboard = new Scoreboard(32) sboard.clear(ll_wen, ll_waddr) - val id_sboard_hazard = checkHazards(hazard_targets, sboard.readBypassed _) + val id_sboard_hazard = checkHazards(hazard_targets, sboard.read _) sboard.set(wb_set_sboard && wb_wen, wb_waddr) // stall for RAW/WAW hazards on CSRs, loads, AMOs, and mul/div in execute stage. @@ -486,7 +486,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) { val ctrl_stalld = id_ex_hazard || id_mem_hazard || id_wb_hazard || id_sboard_hazard || id_ctrl.fp && id_stall_fpu || - id_ctrl.mem && !io.dmem.req.ready || + id_ctrl.mem && Reg(next = !io.dmem.req.ready) || Bool(usingRoCC) && wb_reg_rocc_pending && id_ctrl.rocc && !io.rocc.cmd.ready || id_do_fence || csr.io.csr_stall