From 000e20f93786a86691a13e9dd66907665b14dc0b Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 2 May 2016 15:18:41 -0700 Subject: [PATCH] Remove MIPI; make mip.MSIP read-only The PRCI block outside the core will provide IPIs eventually --- rocket/src/main/scala/csr.scala | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/rocket/src/main/scala/csr.scala b/rocket/src/main/scala/csr.scala index 41efa30f..b9ac2b65 100644 --- a/rocket/src/main/scala/csr.scala +++ b/rocket/src/main/scala/csr.scala @@ -144,7 +144,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p) val reg_mie = Reg(init=UInt(0, xLen)) val reg_mideleg = Reg(init=UInt(0, xLen)) val reg_medeleg = Reg(init=UInt(0, xLen)) - val reg_mip = Reg(init=new MIP().fromBits(0)) + val reg_mip = Reg(new MIP) val reg_mepc = Reg(UInt(width = vaddrBitsExtended)) val reg_mcause = Reg(Bits(width = xLen)) val reg_mbadaddr = Reg(UInt(width = vaddrBitsExtended)) @@ -201,7 +201,6 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p) CSRs.misa -> UInt(isa), CSRs.mstatus -> read_mstatus, CSRs.mtvec -> reg_mtvec, - CSRs.mipi -> reg_mip.msip, CSRs.mip -> read_mip, CSRs.mie -> reg_mie, CSRs.mideleg -> reg_mideleg, @@ -415,10 +414,6 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p) reg_mip.ssip := new_mip.ssip reg_mip.stip := new_mip.stip } - reg_mip.msip := new_mip.msip - } - when (decoded_addr(CSRs.mipi)) { - reg_mip.msip := wdata(0) } when (decoded_addr(CSRs.mie)) { reg_mie := wdata & supported_interrupts } when (decoded_addr(CSRs.mepc)) { reg_mepc := ~(~wdata | (coreInstBytes-1)) }