rocket-chip/.gitmodules

[submodule "uncore"]
	path = uncore
	url = https://github.com/ucb-bar/uncore.git
[submodule "dramsim2"]
	path = dramsim2
	url = https://github.com/dramninjasUMD/DRAMSim2.git
[submodule "riscv-tools"]
	path = riscv-tools
	url = https://github.com/ucb-bar/riscv-tools.git
[submodule "rocket"]
	path = rocket
	url = https://github.com/ucb-bar/rocket.git
[submodule "chisel"]
	path = chisel
	url = https://github.com/ucb-bar/chisel.git
[submodule "hardfloat"]
	path = hardfloat
	url = https://github.com/ucb-bar/berkeley-hardfloat.git
[submodule "fpga-zynq"]
	path = fpga-zynq
	url = https://github.com/ucb-bar/fpga-zynq.git
[submodule "zscale"]
	path = zscale
	url = https://github.com/ucb-bar/zscale
initial commit, all the relevant submodules 2012-09-26 17:46:17 -07:00			`[submodule "uncore"]`
			`path = uncore`
change submodule pointers to https 2014-10-07 03:16:20 -07:00			`url = https://github.com/ucb-bar/uncore.git`
Added dramsim2 memory model to the emulator backend 2012-10-14 14:06:28 -07:00			`[submodule "dramsim2"]`
			`path = dramsim2`
change submodule pointers to https 2014-10-07 03:16:20 -07:00			`url = https://github.com/dramninjasUMD/DRAMSim2.git`
add submodule riscv-tools 2013-05-10 11:53:55 -07:00			`[submodule "riscv-tools"]`
			`path = riscv-tools`
change submodule pointers to https 2014-10-07 03:16:20 -07:00			`url = https://github.com/ucb-bar/riscv-tools.git`
Canonicalized sbt, updated makefiles, cleaned up submodules, minor bugfixes 2013-08-19 19:54:41 -07:00			`[submodule "rocket"]`
			`path = rocket`
change rocket submodule 2014-10-07 03:19:48 -07:00			`url = https://github.com/ucb-bar/rocket.git`
add chisel and hardfloat back as sub-projects, bump other sub-projects 2013-09-26 12:01:46 -07:00			`[submodule "chisel"]`
			`path = chisel`
change submodule pointers to https 2014-10-07 03:16:20 -07:00			`url = https://github.com/ucb-bar/chisel.git`
add berkeley-hardfloat as submodule 2014-09-08 00:18:49 -07:00			`[submodule "hardfloat"]`
			`path = hardfloat`
change submodule pointers to https 2014-10-07 03:16:20 -07:00			`url = https://github.com/ucb-bar/berkeley-hardfloat.git`
add new fpga-zynq as submodule 2014-09-30 09:31:38 -07:00			`[submodule "fpga-zynq"]`
			`path = fpga-zynq`
change submodule pointers to https 2014-10-07 03:16:20 -07:00			`url = https://github.com/ucb-bar/fpga-zynq.git`
add zscale only supports generating Verilog, which plugs into the fpga-spartan6 repository, for now 2015-07-07 20:38:47 -07:00			`[submodule "zscale"]`
			`path = zscale`
			`url = https://github.com/ucb-bar/zscale`