riscv/rocket-chip
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rocket-chip/.gitmodules

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initial commit, all the relevant submodules
2012-09-27 02:46:17 +02:00
[submodule "uncore"]
path = uncore
change submodule pointers to https
2014-10-07 12:16:20 +02:00
url = https://github.com/ucb-bar/uncore.git
Added dramsim2 memory model to the emulator backend
2012-10-14 23:06:28 +02:00
[submodule "dramsim2"]
path = dramsim2
change submodule pointers to https
2014-10-07 12:16:20 +02:00
url = https://github.com/dramninjasUMD/DRAMSim2.git
add submodule riscv-tools
2013-05-10 20:53:55 +02:00
[submodule "riscv-tools"]
path = riscv-tools
change submodule pointers to https
2014-10-07 12:16:20 +02:00
url = https://github.com/ucb-bar/riscv-tools.git
Canonicalized sbt, updated makefiles, cleaned up submodules, minor bugfixes
2013-08-20 04:54:41 +02:00
[submodule "rocket"]
path = rocket
change rocket submodule
2014-10-07 12:19:48 +02:00
url = https://github.com/ucb-bar/rocket.git
add chisel and hardfloat back as sub-projects, bump other sub-projects
2013-09-26 21:01:46 +02:00
[submodule "chisel"]
path = chisel
change submodule pointers to https
2014-10-07 12:16:20 +02:00
url = https://github.com/ucb-bar/chisel.git
add berkeley-hardfloat as submodule
2014-09-08 09:18:49 +02:00
[submodule "hardfloat"]
path = hardfloat
change submodule pointers to https
2014-10-07 12:16:20 +02:00
url = https://github.com/ucb-bar/berkeley-hardfloat.git
add new fpga-zynq as submodule
2014-09-30 18:31:38 +02:00
[submodule "fpga-zynq"]
path = fpga-zynq
change submodule pointers to https
2014-10-07 12:16:20 +02:00
url = https://github.com/ucb-bar/fpga-zynq.git
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