2014-08-31 20:26:55 -07:00
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#=======================================================================
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# Makefile for Verilog simulation w/ VCS
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#-----------------------------------------------------------------------
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# Yunsup Lee (yunsup@cs.berkeley.edu)
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#
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# This makefile will build a rtl simulator and run various tests to
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# verify proper functionality.
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#
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default: all
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base_dir = $(abspath ..)
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generated_dir = $(abspath ./generated-src)
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2014-09-08 00:21:57 -07:00
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mem_gen = $(base_dir)/vsim/vlsi_mem_gen
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2014-08-31 20:26:55 -07:00
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sim_dir = .
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output_dir = $(sim_dir)/output
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2014-09-17 10:48:56 -07:00
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BACKEND ?= rocketchip.RocketChipBackend
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CONFIG ?= DefaultVLSIConfig
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2015-07-17 12:02:02 -07:00
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TB ?= rocketTestHarness
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2014-09-08 00:21:57 -07:00
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2014-09-03 17:28:45 -07:00
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include $(base_dir)/Makefrag
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2014-09-04 09:49:57 -07:00
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include $(sim_dir)/Makefrag
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2015-11-12 00:41:55 -08:00
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ifneq ($(MAKECMDGOALS),clean)
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2015-07-28 00:23:31 -07:00
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-include $(generated_dir)/$(MODEL).$(CONFIG).d
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2015-11-12 00:41:55 -08:00
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endif
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2015-07-28 00:23:31 -07:00
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include $(base_dir)/vsim/Makefrag-verilog
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2014-08-31 20:26:55 -07:00
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all: $(simv)
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2014-09-11 22:11:58 -07:00
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debug: $(simv_debug)
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2014-08-31 20:26:55 -07:00
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clean:
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2014-09-04 09:49:57 -07:00
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rm -rf $(junk) simv* csrc *.key DVE* *.h *.a *.daidir $(generated_dir)
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2014-09-11 22:11:58 -07:00
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.PHONY: default all debug clean
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