2014-09-01 05:26:55 +02:00
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#=======================================================================
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# Makefile for Verilog simulation w/ VCS
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#-----------------------------------------------------------------------
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# Yunsup Lee (yunsup@cs.berkeley.edu)
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#
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# This makefile will build a rtl simulator and run various tests to
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# verify proper functionality.
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#
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default: all
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base_dir = $(abspath ..)
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generated_dir = $(abspath ./generated-src)
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mem_gen = $(base_dir)/fsim/fpga_mem_gen
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sim_dir = .
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output_dir = $(sim_dir)/output
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2014-09-17 19:48:56 +02:00
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BACKEND ?= fpga
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CONFIG ?= DefaultFPGAConfig
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2015-07-17 21:02:02 +02:00
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TB ?= rocketTestHarness
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2014-09-08 09:21:57 +02:00
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2014-09-04 02:28:45 +02:00
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include $(base_dir)/Makefrag
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2014-09-04 18:49:57 +02:00
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include $(sim_dir)/Makefrag
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2016-01-31 05:56:00 +01:00
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ifneq ($(MAKECMDGOALS),clean)
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2015-07-28 09:23:31 +02:00
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-include $(generated_dir)/$(MODEL).$(CONFIG).d
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2016-01-31 05:56:00 +01:00
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endif
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2015-07-28 09:23:31 +02:00
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include $(base_dir)/vsim/Makefrag-verilog
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2014-09-01 05:26:55 +02:00
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all: $(simv)
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2014-09-12 07:11:58 +02:00
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debug: $(simv_debug)
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2014-09-01 05:26:55 +02:00
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clean:
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2014-09-04 18:49:57 +02:00
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rm -rf $(junk) simv* csrc *.key DVE* *.h *.a *.daidir $(generated_dir)
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2014-09-12 07:11:58 +02:00
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.PHONY: default all debug clean
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